VSC7511 datasheet(192/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

177

4.6

PCIe Endpoint Controller

The device implements a single-lane PCIe 1.x endpoint that can be hooked up to any PCIe capable

system. Using the PCIe interface, an external CPU can access (and control) the device. Ethernet frames

can be injected and extracted using registers or the device can be configured to DMA Ethernet frames

autonomously to/from PCIe memory.

Both the VCore-Ie CPU and Frame DMA can generate PCIe read/write requests to any 32-bit or 64-bit

memory region in PCIe memory space. However, it is up to software running on an external CPU to set

up or communicate the appropriate PCIe memory mapping information to the device.

The defaults for the endpoints capabilities region and the extended capabilities region are listed in the

registers list’s description of the PCIE registers. The most important parameters are:

•

Vendor (and subsystem vendor) ID: 0x101B, Microsemi

•

Device ID: 0xB005, device family ID

•

Revision ID: 0x00, device family revision ID

•

Class Code: 0x028000, Ethernet Network controller

•

Single function, non-Bridge, INTA and Message Signaled Interrupt (MSI) capable device

The device family 0xB005 covers several register-compatible devices. The software driver must

determine actual device ID and revision by reading DEVCPU_GCB::CHIP_ID from the device’s memory

mapped registers region.

For information about base address registers, see Base Address Registers, Inbound Requests.

The IDs, class code, revision ID, and base address register setups can be customized before enabling

the PCIe endpoint. However, it requires a manual bring-up procedure by software running locally on the

VCore-Ie CPU. For more information, see Enabling the Endpoint.

The endpoint is power management capable and implements PCI Bus Power Management Interface

Specification Revision 1.2. For more information, see Power Management.

The endpoint is MSI capable. Up to four 64-bit messages are supported. Messages can be generated on

rising and falling edges of each of the two external VCore-Ie interrupt destinations. For more information,

see Outbound Interrupts.

For information about all PCI Express capabilities and extended capabilities register defaults, see the

PCIE region’s register descriptions.

4.6.1

Accessing Endpoint Registers

The root complex accesses the PCIe endpoint’s configuration registers by PCIe CfgRd/CfgWr requests.

The VCore-Ie CPU can read configuration registers by means of the PCIE region. For more information,

see Chip Register Region. The PCIE region must not be accessed when the PCIe endpoint is disabled.

The PCIe region is used during manual bring-up of PCIe endpoint. By using this region, it is possible to

write most of the endpoint’s read-only configuration registers, such as Vendor ID. The PCIe endpoint’s

read-only configuration register values must not be changed after the endpoint is enabled.

The VCore-Ie has a few dedicated PCIe registers in the ICPU_CFG:PCIE register group. An external

CPU attached through the PCIe interface has to go through BAR0 to reach these registers.

4.6.2

Enabling the Endpoint

The PCIe endpoint is disabled by default. It can be enabled automatically or manually by either setting

the VCore_CFG strapping pins or by software running in the VCore-Ie CPU.

The recommended approach is using VCore_CFG strapping pins, because it is fast and does not require

special software running on the VCore-Ie CPU. The endpoint is ready approximately 50 ms after release

of the device’s nRESET. Until this point, the device ignores any attempts to do link training, and the PCIe

output remains idle (tri-stated).

By using software running on the VCore-Ie CPU, it is possible to manually start the PCIe endpoint. Note

that PCIe standard specifies a maximum delay from nRESET release to working PCIe endpoint so

software must enable the endpoint as part of the boot process.

VSC7511 Datasheet(PDF) 192 Page - Microsemi Corporation

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