VSC7511 datasheet(191/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

176

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If the second read is equal to 0x88888888, then the VA logic may have been busy during the read

and additional actions are required: First read the VA_CTRL.VA_BUSY field until the field is cleared

(VA logic is not busy). Then read VA_DATA_INERT. If VA_DATA_INERT returns 0x88888888, then

read-data is actually 0x88888888, continue to the next read. Otherwise, repeat the last read from

VA_DATA, VA_DATA_INCR, or VA_DATA_INERT and then continue to the next read from there.

Optimized reading can be used for single read and sequential read access. For sequential reads, the

VA_ADDR is only incremented on successful (non-busy) reads.

4.5.5

Mailbox and Semaphores

This section provides information about the semaphores and mailbox features for CPU to CPU

communication. The following table lists the registers associated with mailbox and semaphores.

The mailbox is a 32-bit register that can be set and cleared atomically using any CPU interface (including

the VCore-Ie CPU). The MAILBOX register allows reading (and writing) of the current mailbox value.

Atomic clear of individual bits in the mailbox register is done by writing a mask to MAILBOX_CLR. Atomic

setting of individual bits in the mailbox register is done by writing a mask to MAILBOX_SET.

The device implements two independent semaphores. The semaphores are part of the Switch Core

ownership can be taken by interfaces attached to the CSR. That is, the VCore-Ie, VRAP, SI, and MIIM

can be granted ownership.

Any CPU attached to an interface can attempt to take a semaphore n by reading SEMA0.SEMA0 or

SEMA1.SEMA1. If the result is 1, the corresponding semaphore was successfully taken and is now

owned by that interface. If the result is 0, the semaphore was not free. After successfully taking a

semaphore, all additional reads from the corresponding register will return 0. To release a semaphore,

write 1 to SEMA0.SEMA0 or SEMA1.SEMA1.

Note Any interface can release semaphores; it does not have to be the one that has taken the

semaphore. This allows implementation of handshaking protocols.

The current status for a semaphore is available in SEMA0_OWNER.SEMA0_OWNER and

SEMA1_OWNER.SEMA1_OWNER. See register description for encoding of owners.

Software interrupt is generated when semaphores are free or taken. Interrupt polarity is configured

through SEMA_CFG.SEMA_INTR_POL. Semaphore 0 is hooked up to SW0 interrupt and semaphore 1

is hooked up to SW1 interrupt. For configuration of software-interrupt, see Interrupt Controller.

In addition to interrupting on semaphore state, software interrupt can be manually triggered by writing

directly to the ICPU_CFG::INTR_FORCE register.

Software interrupts (SW0 and SW1) can be individually mapped to either the VCore-Ie CPU or to

external interrupt outputs (to an external CPU).

Table 140 •

Mailbox and Semaphore Registers

Description

DEVCPU_ORG::MAILBOX_SET

Atomic set of bits in the mailbox register.

DEVCPU_ORG::MAILBOX_CLR

Atomic clear of bits in the mailbox register.

DEVCPU_ORG::MAILBOX

Current mailbox state.

DEVCPU_ORG::SEMA_CFG

Configuration of semaphore interrupts.

DEVCPU_ORG::SEMA0

Taking of semaphore 0.

DEVCPU_ORG::SEMA1

Taking of semaphore 1.

DEVCPU_ORG::SEMA0_OWNER

Current owner of semaphore 0.

DEVCPU_ORG::SEMA1_OWNER

Current owner of semaphore 1.

VSC7511 Datasheet(PDF) 191 Page - Microsemi Corporation

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