VSC7511 datasheet(194/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

179

PCIE_CFG.PCIE_BAR_WR_ENA = 0

To optionally change selected PCIe configuration space values:

•

Write Vendor ID/Device ID using DEVICE_ID_VENDOR_ID.

•

Write Class Code/Revision ID using CLASS_CODE_REVISION_ID.

•

Write Subsystem ID/Subsystem Vendor ID using SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID.

Enable automatic link training for PCIe endpoint

PCIE_CFG.LTSSM_DIS = 0

The last step enables the endpoint for link training, and the root complex will then be able to initialize the

PCIe endpoint. After this the PCIE parameters must not be changed anymore.

4.6.3

Base Address Registers Inbound Requests

The device implements two memory regions. Read and write operations using the PCIe are translated

directly to read and write access on the SBA. When manually bringing up the PCIe endpoint, BAR1 can

be disabled. For more information, see Manually Starting MAC/PCS and SerDes.

This region supports all access types.

To access the BAR1 region, a Flash must be attached to the SI interface of the device. For information

about how to set up I/O timing and to program the Flash through BAR0; the Chip Registers Region, see

SI Boot Controller, page 191.

4.6.4

Outbound Interrupts

The device supports both Message Signaled Interrupt (MSI) and Legacy PCI Interrupt Delivery. The root

complex configures the desired mode using the MSI enable bit in the PCIe MSI Capability Register Set.

For information about the VCore-Ie interrupt controller, see Interrupt Controller, page 215.

The following table lists the device registers associated PCIe outbound interrupts.

In legacy mode, one interrupt is supported; select either EXT_DST0 or EXT_DST1 using

PCIE_INTR_COMMON_CFG.LEGASY_MODE_INTR_SEL. The PCIe endpoint uses Assert_INTA and

Deassert_INTA messages when configured for legacy mode.

In MSI mode, both EXT_DST interrupts can be used. EXT_DST0 is configured though

PCIE_INTR_CFG[0] and EXT_DST1 through PCIE_INTR_CFG[1]. Enable message generation on rising

and/or falling edges in PCIE_INTR_CFG[n].INTR_RISING_ENA and

PCIE_INTR_CFG[n].INTR_FALLING_ENA. Different vectors can be generated for rising and falling

Table 142 •

Base Address Registers

Description

BAR0, 32-bit, 32 megabytes

Chip registers region. This region maps to the Chip registers

region in the SBA address space. See Chip Register Region.

This region only supports 32-bit word-aligned reads and

writes. Single and burst accesses are supported.

BAR1, 32-bit, 16 megabytes

SI Flash region. This region maps to the SI Flash region in the

SBA address space. See SI Flash Region.

This region only supports 32-bit word-aligned reads. Single

and burst access is supported.

Table 143 •

PCIe Outbound Interrupt Registers

Description

ICPU_CFG::PCIE_INTR_COMMON_CFG Interrupt mode and enable

ICPU_CFG::PCIE_INTR_CFG

MSI parameters

VSC7511 Datasheet(PDF) 194 Page - Microsemi Corporation

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