VSC7511 datasheet(197/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

182

power state changes and then have the VCore-Ie CPU software make application-specific changes to

the device operation depending on the power management state.

Because the device does not implement a dedicated auxiliary power for the PCIe endpoint, the endpoint

is operated from the VDD core power supply. Before the power management driver initializes the device,

software can “force” auxiliary power detection by writing PCIE_AUX_CFG = 3, which causes the

endpoint to report that it is capable of emitting Power Management Events (PME) messages in the D3c

state.

The current device power management state is available using PCIE_STAT.PM_STATE. A change in this

field’s value sets the PCIE_INTR.INTR_PM_STATE sticky bit. To enable this interrupt, set

PCIE_INTR_ENA.INTR_PM_STATE_ENA. The current state of the PCIe endpoint interrupt towards the

VCore-Ie interrupt controller is shown in PCIE_INTR_IDENT register (if different from zero, then interrupt

is active).

The endpoint can emit PMEs if the PME_En bit is set in the PM Capability Register Set and if the

endpoint is in power-down mode.

•

Outbound request from either SBA or FDMA trigger PME.

•

A change in status for an enabled outbound interrupt (either legacy or MSI) triggers PME. This

feature can be disabled by setting

ICPU_CFG::PCIE_INTR_COMMON_CFG.WAKEUP_ON_INTR_DIS.

In the D3 state, the endpoint transmits a beacon. The beacon function can be disabled and instead drive

the WAKE output using the overlaid GPIO function. For more information about the overlaid function on

the GPIO for this signal, see GPIO Overlaid Functions, page 204.

Enable WAKE by setting PCIEPCS_CFG.BEACON_DIS. The polarity of the WAKE output is configured

in PCIEPCS_CFG.WAKE_POL. The drive scheme is configured in PCIEPCS_CFG.WAKE_OE.

4.6.7

Device Reset Using PCIe

The built-in PCIe reset mechanism in the PCIe endpoint resets only the PCIe MAC. The device reset is

not tied into the MAC reset. To reset the complete the device, use the following procedure.

Save the state of the PCIe controller registers using operating system.

Set DEVCPU_GCB::SOFT_RST.SOFT_CHIP_RST.

Wait for 100 ms.

Recover state of PCIe controller registers using operating system.

Setting SOFT_CHIP_RST will cause re-initialization of the device.

Table 147 •

Power Management Registers

Description

ICPU_CFG::PCIE_STAT

Current power management state

ICPU_CFG::PCIEPCS_CFG

Configuration of WAKE output and beacon

ICPU_CFG::PCIE_INTR

PCIe interrupt sticky events

ICPU_CFG::PCIE_INTR_ENA

Enable of PCIe interrupts

ICPU_CFG::PCIE_INTR_IDENT

Currently interrupting PCIe sources

ICPU_CFG::PCIE_AUX_CFG

Configuration of auxiliary power detection

Table 148 •

PCIe Wake Pin

Pin Name

I/O

Description

PCIe_WAKE/GPIO

PCIe WAKE output

VSC7511 Datasheet(PDF) 197 Page - Microsemi Corporation

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