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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

142

3.14.1

Frame Extraction

The following table lists the registers associated with frame extraction.

In the switch core, CPU extracted frames are forwarded to one of the eight CPU extraction queues. Each

of these queues is mapped to one of two CPU ports (port 11 and port 12) through

QSYS::CPU_GROUP_MAP. For each CPU port, there is a scheduler working either in strict mode or

round robin, which selects between the CPU extraction queues mapped to the same CPU port. In strict

mode, higher queue numbers are preferred over smaller queue numbers. In round robin, all queue are

serviced one after another.

The two CPU ports contain the same rewriter as regular front ports. The rewriter modifies the frames

before sending them to the CPU. In particular, the rewriter inserts an extraction header

(SYS::PORT_MODE.INCL_XTR_HDR), which contains relevant side band information about the frame

such as the frame’s classification result (VLAN tag information, DSCP, QoS class), ingress time stamp,

and the reason for sending the frame to the CPU. For more information about the rewriter, see Rewriter,

page 133.

The device CPU contains the functionality for reading out the frames. This can be done through the

frame DMA or regular register access. The Versatile Register Access Protocol (VRAP) Engine can also

be attached to one of the CPU extraction groups. This allows an external device to access internal

registers through Ethernet frames.

The following table lists the contents of the CPU extraction header.

Table 113 •

Frame Extraction Registers

Description

Replication

QSYS::CPU_GROUP_MAP

Configuration of mapping of extraction

queues to CPU ports.

None

SYS::PORT_MODE.INCL_XTR_HDR Enables insertion of extraction header.

Configures formatting of outgoing

frames.

Per CPU port

(ports 11 and 12)

Table 114 •

CPU Extraction Header

Field

Bit

Width

Description

RESERVED

127

Reserved.

REW_OP

117

Rewriter operation command.

REW_OP[2:0] = 3 implies two-step PTP where REW_OP[8:3]

contains the PTP time stamp identifier.

Other settings do not apply.

REW_VAL

This field contains the Rx time when the frame was received.

LLEN

Frame length in bytes: 60 × WLEN + LLEN – 80.

WLEN

See LLEN.

RESERVED

Reserved.

SRC_PORT

The port number where the frame was received (0-11).

ACL_ID

If ACL_HIT is set, this value is the combined ACL_ID action of

the rules hit in IS2.

RESERVED

Reserved.

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