VSC7511 datasheet(158/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

143

3.14.2

Frame Injection

The following table lists the registers associated with frame injection.

The CPU injects frames through the two CPU injection groups that are independent of each other. The

injection groups connect to the two CPU ports (port 11 and port 12) in the CPU port module. In CPU port

module, each of the two CPU ports have dedicated access to the switch core. Inside the switch core, all

CPU injected frames are seen as coming from CPU port (port 11). This implies that both CPU injection

groups consume memory resources from the shared queue system for port 11 and that analyzer

configuration for port 11 are applied to all frames.

In the switch core, the CPU port can be preferred over other ingress ports when transferring frames to

egress queues by enabling precedence of the CPU port (QSYS::EQ_PREFER_SRC).

SFLOW_ID

sFlow sampling ID.

0-11: Frame was sFlow sampled by a Tx sampler on port given

by SFLOW_ID.

12: Frame was sFlow sampled by an Rx sampler on port given

by SRC_PORT.

13-14: Reserved.

15: Frame was not sFlow sampled.

ACL_HIT

Set if frame has hit a rule in IS2, which copies the frame to the

CPU (IS2 actions CPU_COPY_ENA or HIT_ME_ONCE).

The frame’s drop precedence (DP) level after policing.

LRN_FLAGS

The source MAC address learning action triggered by the frame.

0: No learning.

1: Learning of a new entry.

2: Updating of an already learned unlocked entry.

3: Updating of an already learned locked entry.

CPUQ

CPU extraction queue mask (one bit per CPU extraction queue).

Each bit set implies the frame was subjected to CPU forwarding

to the specific queue.

QOS_CLASS

The frame’s classified QoS class.

TAG_TYPE

The tag information’s associated Tag Protocol Identifier (TPID).

The definitions are:

0: C-tag: EtherType = 0x8100.

1: S-tag: EtherType = 0x88A8 or custom value.

PCP

The frame’s classified PCP.

DEI

The frame’s classified DEI.

VID

The frame’s classified VID.

Table 115 •

Frame Injection Registers

Description

Replication

SYS::PORT_MODE.INCL_INJ_HDR Enable parsing of injection header.

Configures formatting of incoming frames.

Per CPU port

(ports 11 and 12)

QSYS::EQ_PREFER_SRC

Enable preferred arbitration of the CPU

port (port 11) over front ports.

CPU port (port 11

only)

Table 114 •

CPU Extraction Header (continued)

Field

Bit

Width

Description

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