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VSC7511 Datasheet(PDF) 162 Page - Microsemi Corporation |
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VSC7511 Datasheet(HTML) 162 Page - Microsemi Corporation |
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162 / 324 page  Functional Descriptions VMDS-10488 VSC7511 Datasheet Revision 4.2 147 Figure 45 • CPU Injection and Extraction Prefixes Note that inserting a CPU extraction header in front of a frame disables all other frame modifications done in the rewriter. When injecting frames with an CPU injection header all incoming frames are expected to adhere to the configured prefix mode. The following parsing of the frames takes place: • No prefix. All incoming frames are parsed as if they have a CPU injection header in front of the frame. Forwarding is based on the instructions in the CPU injection header. • Short prefix. Incoming frames are checked against the expected format (start of frame must include 0x8880000A). If the prefix does not match then an error indication is set (SYS::PORT_MODE.INJ_HDR_ERR). Compliant frames are forwarded based on the instructions in the CPU injection header. Non-compliant frames are forwarded as normal frames where the prefix and CPU injection header equaling the first 20 bytes of the frame are skipped. • Long prefix. All incoming frames are parsed as if they have a long prefix followed by the CPU injection header in front of the frame. The incoming frames are checked against the expected format (start of frame must include 12 bytes of MAC addresses followed by 0x8880000A). If the prefix does not match then an error indication is set (SYS::PORT_MODE.INJ_HDR_ERR). Both compliant and non-compliant frames are forwarded based on the instructions in the CPU injection header. The external CPU can control forwarding of injected frames by either letting the frame analyze and forward accordingly or directly specifying the destination set. This is controlled through the BYPASS field in the CPU injection header. 3.14.4 Frame Generation Engine for Periodic Transmissions The following table lists the registers associated with the frame generation engine. Table 118 • Frame Generation Engine Register Description Replication QSYS::TFRM_MISC Configuration to cancel ongoing periodic transmissions. None QSYS::TFRM_PORT_DLY_ENA Enable spaced-out transmissions when multiple periodic transmissions are scheduled at the same time. Per port QSYS::TFRM_TIMER_CFG_x Period configuration. These registers configure the transmission period between frames. 8 FF-FF-FF-FF-FF-FF 48 bits FE-FF-FF-FF-FF-FF 48 bits 8880 16 bits 000A 16 bits CPU Extraction header 128 bits Extraction with long prefix: Extraction with short prefix: Extraction with no prefix: Original frame Any DMAC 48 bits Any SMAC 48 bits 8880 16 bits 000A 16 bits CPU Injection header 128 bits Injection with long prefix: 8880 16 bits 000A 16 bits CPU Injection header 128 bits Original frame Injection with short prefix: CPU Injection header 128 bits Injection with no prefix: Original frame Original frame 8880 16 bits 000A 16 bits CPU Extraction header 128 bits Original frame CPU Extraction header 128 bits Original frame Start-of-frame |
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