VSC7511 datasheet(163/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

148

The device contains a frame generation engine that can periodically transmit frames on a port with a

programmable transmission period. The transmission period can be as low as 200 ns, which implies

wire-speed back-to-back transmissions, or as high as several minutes. Up to 1024 periodic

transmissions can coexist with up to eight different transmission periods.

To set up a periodic transmission, the CPU must inject a setup frame using the following settings in the

injection header:

•

REW_VAL set to the selected transmission slot (0 through 1023).

•

ACL_ID set to the selected timer (1 through 8). The transmission period is programmed in steps of

198.2 ns in TFRM_TIMER_CFG_x, where x = ACL_ID. Note that injecting a frame with ACL_ID > 0

effectively enables the periodic transmissions. To inject a normal frame, ACL_ID must be set to 0.

•

BYPASS set to 1.

•

DEST set to the Tx port to which the periodic transmission applies. Only one Tx port per

transmission is possible.

•

Other fields in the injection header are applicable the same way as for normal injections. Note, that

the periodic transmissions are subject to normal rewriter operations before being transmitted on the

Tx port. For more information, see Rewriter, page 133.

After the injection, the setup frame is placed into the selected transmission slot and it is periodically

transmitted using the transmission period defined by the selected timer. Every time the transmission

period has passed since the last transmission, the frame is scheduled for a new transmission on the

associated port. The periodic frame transmission takes precedence over other transmissions on the port,

and as a consequence the frame is transmitted immediately after a potential ongoing transmission has

ended.

If multiple periodic transmissions on a Tx port use the same timer, multiple frames are scheduled for

transmission at the same time when the period has passed. By default, these frames are transmitted in a

burst, back-to-back. However, it is also possible to space-out these frames over time and thereby

allowing the normal data traffic to be interleaved the periodic transmissions. If the spacing is enabled

(TFRM_PORT_DLY), timer 8 defines the period between frames in the burst.

Periodic transmissions are cancelled again by programming the slot number in

TFRM_MISC.TIMED_CANCEL_SLOT and setting TFRM_MISC.TIMED_CANCEL_1SHOT. This

removes the injected frame from the transmission slot.

Transmission slots 0 through 15 support any transmission periods including back-to-back transmissions

while slots 16 through 1023 support transmission periods larger than 30 µs.

Frames transmitted from the frame generation engine are counted by the Tx counters just like normal

frames using the QoS class specified in the injection header by the setup frame.

3.15

VRAP Engine

The Versatile Register Access Protocol (VRAP) engine allows external equipment to access registers in

the device through any of the Ethernet port’s on the device. The VRAP engine interprets incoming VRAP

requests, and executes read, write, and read-modify-write commands contained in the frames. The

results of the register accesses are reported back to the transmitter through automatically generated

VRAP response frames.

The device supports version 1 of VRAP. All VRAP frames, both requests and responses, are standard

Ethernet frames. All VRAP protocol fields are big-endian formatted.

The registers listed in the following table control the VRAP engine.

Table 119 •

VRAP Registers

Target:Register_group:Register.field

Description

Replication

ANA:CPU_FWD_CFG:CPU_VRAP_REDIR_ENA Enable redirection of VRAP frames

to CPU.

Per port

ANA:CPUQ_CFG2:CPUQ_VRAP

Configure the CPU extraction queue

for VRAP frames.

None

VSC7511 Datasheet(PDF) 163 Page - Microsemi Corporation

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