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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

149

The VRAP engine processes incoming VRAP frames that are redirected to the VRAP CPU extraction

queue by the basic classifier. For more information about the VRAP filter in the classifier, see CPU

Forwarding Determination, page 58.

The VRAP engine is enabled by allocating one of the two CPU ports as a dedicated VRAP CPU port

(DEVCPU_QS:XTR_GRP_CFG:MODE and DEVCPU_QS:INJ_GRP:MODE). The VRAP CPU

extraction queue (ANA:CPUQ_CFG2:CPUQ_VRAP) must be mapped as the only CPU extraction queue

to the VRAP CPU port (QSYS:CPU_GROUP_MAP:CPU_GROUP_MAP). In addition, the VRAP CPU

port must disable the use of CPU injection and CPU extraction headers

(SYS:PORT_MODE:INCL_INJ_HDR and SYS:PORT_MODE:INCL_XTR_HDR).

The complete VRAP functionality can be enabled automatically at chip startup by the use of special chip

boot modes. For more information, see VCore-Ie Configurations, page 159.

The following describes the VRAP frame formats.

3.15.1

VRAP Request Frame Format

The following illustration shows the format of a VRAP request frame.

Figure 46 •

VRAP Request Frame Format

VRAP request frames can optionally be VLAN tagged with one VLAN tag.

The EtherType = 0x8880 and the Ethernet Protocol Identifier (EPID) = 0x0004 identify the VRAP frames.

The subsequent VRAP header is used in both request and response frames.

The VRAP commands included in the request frame are the actual register access commands. The

VRAP engine supports the following five VRAP commands:

•

READ: Returns the 32-bit contents of any register in the device.

•

WRITE: Writes a 32-bit value to any register in the device.

•

READ-MODIFY-WRITE: Does read/modify/write of any 32-bit register in the device.

•

IDLE: Does not access registers but is useful for padding and identification purposes.

•

PAUSE: Does not access registers but causes the VRAP engine to pause between register access.

Each of the VRAP commands are described in the following sections. Each VRAP request frame can

contain multiple VRAP commands. Commands are processed sequentially starting with VRAP command

#1, #2, and so on. For more information, see <figure reference>. There are no restrictions on the order or

number of commands in the frame.

QSYS:CPU_GROUP_MAP:CPU_GROUP_MAP

Map VRAP CPU extraction queue to

a CPU port. One CPU port must be

reserved for VRAP frames.

None

DEVCPU_QS:XTR_GRP_CFG:MODE

Enable VRAP mode for reserved

CPU port.

Per CPU port

DEVCPU_QS:INJ_GRP_CFG:MODE

Enable VRAP mode injection for

reserved CPU port.

Per CPU port

SYS:PORT_MODE:INCL_INJ_HDR

The injection header is not present

for VRAP response frames.

Per port

SYS:PORT_MODE:INCL_XTR_HDR

The extraction header is not present

for redirected VRAP frames.

Per port

DEVCPU_GCB:VRAP_ACCESS_STAT

VRAP access status.

None

Table 119 •

VRAP Registers (continued)

Target:Register_group:Register.field

Description

Replication

Any valid DMAC

0x8880

DMAC

Any valid SMAC

SMAC

0x0004

EtherType

EPID

Valid FCS

FCS

VRAP Commands

16 bits

48 bits

32 bits

variable length

VRAP HDR

(Request)

32 bits

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