VSC7511 datasheet(167/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

152

3.15.8

VRAP PAUSE Command

The PAUSE command does not access registers in the device. Instead, it causes the VRAP engine to

enter a wait state and remain there until the pause time has expired. This can be used to ensure

sufficient delay between VRAP commands when this is needed.

The PAUSE command is 4 bytes wide and consists of one 32-bit code word with the four least significant

bits of the code word set to 0100. The wait time is controlled by the 28 most significant bits of the wait

command. The time unit is 1 us. The following illustration depicts the PAUSE command.

Figure 53 •

PAUSE Command

3.16

Layer 1 Timing

There are eight recovered clocks, four outputs that provide timing sources for external timing circuitry in

redundant timing implementations, and four internal clocks for the timing-recovery circuit. The following

tables list the registers and pins associated with Layer 1 timing.

It is possible to recover receive timing from any 10/100/1000 Mbps and 2.5 Gbps data streams into the

device.

The recovered clock outputs have individual divider configuration (through

SYNC_ETH_CFG.SEL_RCVRD_CLK_DIV) to allow division of SerDes receive frequency by 1, 2, 4, 5, 8,

16, or 25.

The recovered clocks are single-ended outputs, and the suggested divider settings in the following tables

are selected to make sure to not output too high a frequency through the input and outputs.

The four CuPHY ports share two recovered clocks. In table Table 122, page 153, the two clock resources

are called clk and can take the value 0 or 1. The CLK_SRC_SEL0 and CLK_SRC_SEL1 fields are

Table 120 •

Layer 1 Timing Configuration Registers

Description

HSIO::SYNC_ETH_CFG

Configures recovered clocks. Replicated per recovered clock.

HSIO::SYNC_ETH_PLL_CFG

Additional PLL recovered clock configuration. Replicated per

recovered clock.

HSIO::PLL5G_CFG3

Enables high speed clock output.

PHY:PHY_GP:PHY_RCVD_CLK0_CTRL

Configures PHY recovered clock 0.

PHY:PHY_GP:PHY_RCVD_CLK1_CTRL

Configures PHY recovered clock 1.

Table 121 •

Layer 1 Timing Recovered Clock Pins

Pin Name

I/O

Description

RCVRD_CLK0

Recovered clock output, configured by SYNC_ETH_CFG[0].

This is an overlaid function on GPIO.

RCVRD_CLK1

Recovered clock output, configured by SYNC_ETH_CFG[1].

This is an overlaid function on GPIO.

CLKOUT

PLL high speed clock output.

Pause value (µs)

Request:

32 bits

0100

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