VSC7511 datasheet(171/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

156

In addition, the load operation can load a delta to the current time. This is done by executing a LOAD

action but using the DELTA command.

Each operation generates an interrupt when executed. For the clock action, the interrupt is generated

when the output switches to the active level. The interrupts from each controller can be masked and

monitored by the interrupt controller in the ICPU_CFG register target.

The four controllers are completely equal in their capabilities.

3.17.3

Hardware Time Stamping Module

This section explains the functions of the hardware time stamping module. The following table lists the

registers associated with the hardware time stamping module.

Each port module contains a hardware time stamping module that measures arrival and departure times

based on the master timer. For information about how the Rx and Tx time stamps are derived, see Rx

and Tx Time Stamps, page 21.

3.17.3.1 Two-Step Time Stamping

Two-step time stamping is performed if the IS2 rewriter action is two-step

(IS2_ACTION.REW_OP[2:0] = 3). This action can be applied to any frame, also non-PTP frames,

because the frame itself is not modified. The frame’s Tx time stamp is stored in a time stamp FIFO

queue, which the CPU can access (SYS::PTP_STATUS). The time stamp is common for all egress ports

and can contain up to 128 time stamps. Each entry in the time stamp queue contains the following fields:

•

SYS::PTP_STATUS.PTP_MESS_VLD: A 1-bit valid bit meaning the entry is ready for reading.

•

SYS::PTP_STATUS.PTP_MESS_ID: A 6-bit time stamp identifier. A unique time stamp identifier is

assigned to each frame for which one or more Tx time stamps are generated. The time stamp

identifier is also available in the CPU extraction header for frames extracted to the CPU. The time

stamp identifier overloads the DSCP value in the CPU extraction header. For more information about

the CPU extraction header, see Table 114, page 142. By providing the time stamp identifier in both

the time stamp queue and in the extracted frames, the CPU can correlate which time stamps belong

to which frames. Note that time stamp identifier value 63 implies that no free identifier could be

assigned to the frame. The time stamp entry can therefore not be trusted.

•

SYS::PTP_STATUS.PTP_MESS_TXPORT: The port number where the frame is transmitted. When

transmitting a frame on multiple ports, there are generated multiple entries in the time stamp queue.

Each entry uses the same time stamp identifier but with different Tx port numbers.

•

SYS::PTP_TXSTAMP: The frame’s Tx time stamp.

The time stamp queue is a simple FIFO that can be read by the CPU. The time stamp queue provides the

following handles for reading:

Waveform high

Number of nanoseconds in the high period for generated clocks.

Duration of pulse for generated pulse.

Waveform_low

Number of nanoseconds in the low period for generated clocks.

Delay from TOD_ns = 0 for generated pulse.

Table 127 •

Hardware Time Stamping Registers

Description

Replication

SYS::PTP_TXSTAMP time stamp value in time stamp queue.

None

SYS::PTP_NXT

Advancing the time stamp queue.

None

SYS::PTP_STATUS

time stamp queue status and entry data.

None

ANA::PTP_ID_HIGH

Release of time stamp identifiers, values 32 through 63.

None

ANA::PTP_ID_LOW

Release of time stamp identifiers, values 0 through 31.

None

Table 126 •

LoadStore Controller (continued)

Pin Control Field

Function

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