VSC7511 datasheet(172/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

157

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Overflow of the queue is signaled through SYS::PTP_STATUS.PTP_OVFL. Overflow implies that

one or more time stamps could not be enqueued due to all 128 entries being in use. time stamps not

enqueued are lost.

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The head-of-line entry is read through SYS::PTP_STATUS and SYS::PTP_TXSTAMP.

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Writing to the one-shot register SYS::PTP_NXT, removes the current head-of-line entry and

advances the pointer to the next entry in the time stamp queue.

When two-step Tx time stamping is performed for a frame destined for the CPU extraction queues, no

entry in the time stamp FIFO queue is made. The frame’s Rx time stamp is available through the CPU

extraction header.

The time stamp identifiers can take values between 0 to 63. Value 63 implies that all values 0-62 are in

use. Values 0 – 3 are pre-assigned to the CPU to be used for injection of frames. The remaining values

are assigned by the analyzer to frames requesting time stamping through the VCAP IS2 action. The

assigned values must be released again by the CPU by writing to the corresponding bit in

ANA::PTP_ID_HIGH (values 32 through 63) or ANA::PTP_ID_LOW (values 0 through 31). The CPU

releases a time stamp identifier when it has read the anticipated time stamp entries from the time stamp

queue. Note that multicasted frames generate a time stamp entry per egress port using the same time

stamp identifier. Each of these entries must be read before the time stamp identifier is released.

Two-step time stamping can be disabled per egress port using REW:PORT:PTP_CFG.PTP_2STEP_DIS.

This setting overrules the IS2 action.

3.17.4

Configuring I/O Delays

After a valid link is established and detected by the involved PCS logic, the I/O delays from the internal

time stamping points to the serial line must be configured. The delays are both mode-specific and

interface-specific, depending on the core clock frequency.

Ingress barrel shifter states that in 1G mode, the Rx delays must be added 0.8 ns times the value of

PCS1G_LINK_STATUS.DELAY_VAR to adjust for barrel shifting state after link establishment. In 2.5G

mode, the multiplier is 0.32 ns. In 100FX mode, the Rx delays must be subtracted 0.8 ns times the value

of PCS_FX100_STATUS.EDGE_POS_PTP to adjust for detected data phase.

The Rx and Tx delay values for the different ports and modes are automatically configured in the

software API.

3.18

Clocking and Reset

The reference clock for the PLL (REFCLK_P/N) is either differential or single-ended. The frequency can

be 25 MHz, 125 MHz, 156.25 MHz, or 250 MHz. The PLL must be configured for the appropriate clock

frequency by using strapping inputs REFCLK_CONF[2:0].

The PLL can be used as a recovered clock source for Synchronous Ethernet. For information about how

to configure PLL clock recovery, see Layer 1 Timing, page 152.

For information about protecting the VCore CPU system during a soft-reset, see Clocking and Reset,

page 157.

3.18.1

Pin Strapping

Configure PLL reference clock and VCore startup mode using the strapping pins on the GPIO interface.

The device latches strapping pins and keeps their value when nRESET to the device is released. After

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