VSC7511 datasheet(175/324 Pages) MICROSEMI

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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

160

The strapping value determines the reset value for the ICPU_CFG::GENERAL_CTRL register. After

startup, the behavior of the VCore-Ie system can be modified by changing some of the fields in this

•

After starting the device with the VCore-Ie CPU disabled, an external CPU can manually boot the

VCore-Ie CPU from SI Flash by writing ICPU_CFG::GENERAL_CTRL.IF_SI_OWNER = 1,

ICPU_CFG::GENERAL_CTRL.BOOT_MODE_ENA = 1, and

ICPU_CFG::GENERAL_CTRL.CPU_DIS = 0. Setting GENERAL_CTRL.IF_SI_OWNER disables

the SI slave, so the external CPU must use another interface than SI.

•

After starting the device with the VCore-Ie CPU disabled, the 8051 internal memory can be loaded

with software and the VCore-Ie CPU can be booted as explained in Starting the VCore-Ie CPU,

page 165.

•

After automatically booting from SI Flash, the VCore-Ie CPU can release the SI interface and enable

the SI slave by writing ICPU_CFG::GENERAL_CTRL.IF_SI_OWNER = 0. This enables SI access

from an external CPU to the device. A special PCB design is required to make the serial interface

work for both Flash and external CPU access.

•

MIIM slave can be manually enabled by writing

ICPU_CFG::GENERAL_CTRL.IF_MIIM_SLV_ENA = 1. The MIIM slave automatically takes control

of the appropriate GPIO pins.

4.2

Clocking and Reset

The following table lists the registers associated with reset and the watchdog timer.

The VCore-Ie CPU runs 250 MHz and the rest of the VCore-Ie system runs at 250 MHz.

The VCore-Ie can be soft reset by setting RESET.CORE_RST_FORCE. By default, this resets both the

VCore-Ie CPU and the VCore-Ie system. The VCore-Ie system can be excluded from a soft reset by

setting RESET.CORE_RST_CPU_ONLY; soft reset using CORE_RST_FORCE only then resets the

VCore-Ie CPU. The frame DMA must be disabled prior to a soft reset of the VCore-Ie system. When

CORE_RST_CPU_ONLY is set, the frame DMA and the PCIe endpoint are not affected by a soft reset

and continue to operate throughout soft reset of the VCore-Ie CPU.

The VCore-Ie system comprises all the blocks attached to the VCore Shared Bus (SBA), including the

PCIe and frame DMA/injection/extraction blocks. Blocks attached to the switch core Register Bus (CSR),

including VRAP, SI, and MIIM slaves, are not part of the VCore-Ie system reset domain. For more

information about the VCore-Ie system blocks, see Figure 4.1, page 159.

The device can be soft reset by writing SOFT_RST.SOFT_CHIP_RST. The VCore-Ie system and CPU

can be protected from a device soft reset by writing RESET.CORE_RST_PROTECT = 1 before initiating

a soft reset. In this case, a chip-level soft reset is applied to all other blocks, except the VCore-Ie system

and the CPU. When protecting the VCore-Ie system and CPU from a soft reset, the frame DMA must be

disabled prior to a chip-level soft reset. The SERDES and PLL blocks can be protected from reset by

writing to SOFT_RST.SOFT_SWC_RST instead of SOFT_CHIP_RST.

The VCore-Ie general purpose registers (ICPU_CFG::GPR) and GPIO alternate modes

(DEVCPU_GCB::GPIO_ALT) are not affected by a soft reset. These registers are only reset when an

external reset is asserted.

Table 129 •

Clocking and Reset Configuration Registers

Description

ICPU_CFG::RESET

VCore-Ie reset protection scheme and initiating soft reset of

the VCore-Ie system and/or CPU.

DEVCPU_GCB::SOFT_RST

Initiating chip-level soft reset.

ICPU_CFG::WDT

Watchdog timer configuration and status.

VSC7511 Datasheet(PDF) 175 Page - Microsemi Corporation

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