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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

161

4.2.1

Watchdog Timer

The VCore system has a built-in watchdog timer (WDT) with a two-second timeout cycle. The watchdog

timer is enabled, disabled, or reset through the WDT register. The watchdog timer is disabled by default.

After the watchdog timer is enabled, it must be regularly reset by software. Otherwise, it times out and

cause a VCore soft reset equivalent to setting RESET.CORE_RST_FORCE. Improper use of the

WDT.WDT_LOCK causes an immediate timeout-reset as if the watchdog timer had timed out. The

WDT.WDT_STATUS field shows if the last VCore-Ie CPU reset was caused by WDT timeout or regular

reset (possibly soft reset). The WDT.WDT_STATUS field is updated only during VCore-Ie CPU reset.

To enable or to reset the watchdog timer, write the locking sequence, as described in WDT.WDT_LOCK,

at the same time as setting the WDT.WDT_ENABLE field.

Note: Because watchdog timeout is equivalent to setting RESET.CORE_RST_FORCE, the

RESET.CORE_RST_CPU_ONLY field also applies to watchdog initiated soft reset.

4.3

Shared Bus

The shared bus is a 32-bit address and 32-bit data bus with dedicated master and slave interfaces that

interconnect all the blocks in the VCore-Ie system. The VCore-Ie CPU, PCIe inbound, and VCore SBA

access block are masters on the shared bus; only they can start access on the bus.

The shared bus uses byte addresses, and transfers of 8, 16, or 32 bits can be made. To increase

performance, bursting of multiple 32-bit words on the shared bus can be performed.

All slaves are mapped into the VCore-Ie system’s 32-bit address space and can be accessed directly by

masters on the shared bus. The SI Flash boot master is mirrored into the lowest address region.

Figure 56 •

Shared Bus memory

The Frame DMA has dedicated access to PCIe outbound. This means that access on the SBA to other

parts of the device, such as register access, does not affect Frame DMA injection/extraction

performance.

4.3.1

VCore-Ie Shared Bus Arbitration

The following table lists the registers associated with the shared bus arbitration.

Table 130 •

Shared Bus Configuration Registers

Description

SBA::PL_CPU

Master priorities

SBA::PL_PCIE

Master priorities

Reserved

Mirror of SI Flash

Chip Registers

0x00000000

0x80000000

0x20000000

0xFFFFFFFF

0x10000000

256 MB

1 GB

512 MB

0x00000000

0x80000000

0x20000000

256 MB

0x70000000

SI Flash

0x40000000

256 MB

0x40000000

0x50000000

256 MB

512 MB

0x50000000

PCIe DMA

1 GB

0xC0000000

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