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VCore-Ie System and CPU Interfaces

VMDS-10488 VSC7511 Datasheet Revision 4.2

159

VCore-Ie System and CPU Interfaces

This section provides information about the functional aspects of blocks and interfaces related to the

VCore-Ie on-chip microprocessor system and an external CPU system.

The device contains a fast VCore-Ie CPU system that is based on an embedded 8051-compatible

microprocessor and a high bandwidth Ethernet Frame DMA engine. The VCore-Ie system can control the

device independently, or it can support an external CPU, relieving the external CPU of the otherwise time

consuming tasks of transferring frames, maintaining the switch core, and handling networking protocols.

When the VCore-Ie CPU is enabled, it either automatically boots up from serial Flash or an external CPU

can manually load a code-image to the device and then start the VCore-Ie CPU.

An external CPU can be connected to the device through the PCIe interface, serial interface (SI),

dedicated MIIM slave interface, or through Versatile Register Access Protocol (VRAP) formatted

Ethernet frames using the NPI Ethernet port.

The following illustration shows the VCore-Ie block diagram.

Figure 55 •

VCore-Ie System Block Diagram

4.1

VCore-Ie Configurations

The behavior of the VCore-Ie system after a reset is determined by four VCore strapping pins that are

overlaid on GPIO pins. The value of these GPIOs is sampled shortly after releasing reset to the device.

For more information about the strapping pins, see Pin Strapping, page 157.

Switch Core

Access/Arbiter

Switch Core Register Bus (CSR)

Switch Core

Registers

VCore SBA

Access Block

VCore Shared Bus

Access/Arbiter

VCore Shared Bus (SBA)

GPIO I/O

Controller

MIIM

Masters × 2

Temperature

Sensor

Fan

Controller

SGPIO I/O

Controller

Two-Wire Serial

Interface

UART × 2

Interrupt

Controller

SI Flash Boot

Master(1)

Timers × 3

PCIe Inbound(2)

PCIe

Outbound

VRAP

(Register access

through Ethernet)

Switch Core

Access Block

VCore CPU

MIIM Slave

SI Slave(1)

Frame DMA

(FDMA)

Manual Frame

Inject/Extract

1. When the Vcore-III CPU boots up from the SI Flash, the SI is reserved as boot interface and cannot be used by an external CPU.

2. Inbound PCIe access to BAR0 maps to VCore register space (interrupt controller, timers, two-wire serial master/slave, UARTs, and

manual frame injection/extraction). Switch core access block is not reachable via PCIe inbound accesses.

VSC7511 Datasheet(PDF) 174 Page - Microsemi Corporation

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