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VSC7511 Datasheet(PDF) 161 Page - Microsemi Corporation

Part # VSC7511
Description  4-Port Layer-2 Gigabit Ethernet Switch
PDF  324 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7511 Datasheet(HTML) 161 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10488 VSC7511 Datasheet Revision 4.2
146
3.14.3
Node Processor Interface (NPI)
The following table lists the registers associated with the NPI.
Any front port can be configured as an NPI through which frames can be injected from and extracted to
an external CPU. Only one port can be an NPI at the same time.
QSYS::EXT_CPU_CFG.EXT_CPU_PORT holds the port number of the NPI.
A dual CPU system is possible where both the internal and the external CPU are active at the same time.
Through QSYS::EXT_CPU_CFG.EXT_CPUQ_MSK, it is configurable to which of the eight CPU
extraction queues are directed to the internal CPU and which are directed to external CPU. A frame can
be extracted to both the internal CPU and the external CPU if the frame is extracted for multiple reasons.
Frames being extracted by the external CPU can have the CPU extraction header inserted in front of the
frame (SYS::PORT_MODE.INCL_XTR_HDR). Similarly, frames being injected into the switch core by the
external CPU can have the CPU injection header inserted in front of the frame
(SYS::PORT_MODE.INCL_INJ_HDR). In addition, there three different options in terms of inserting a
prefix in front of the CPU injection or extraction header. The following illustration shows the different
frame formats supported.
POP_CNT
28
2
Number of VLAN tags that must be popped in the rewriter before
adding new tags. Used when BYPASS = 1.
0: No tags must be popped.
1: One tag must be popped.
2: Two tags must be popped.
3: Disable all rewriting of the frame. The rewriter can still update
the FCS.
CPUQ
20
8
CPU extraction queue mask (one bit per CPU extraction queue).
Each bit set implies the frame must be forwarded by the CPU to
the specific queue.
Used when BYPASS = 1 and DEST[11] = 1.
QOS_CLASS
17
3
The frame’s classified QoS class.
Used when BYPASS = 1.
TAG_TYPE
16
1
The tag information’s associated Tag Protocol Identifier (TPID).
Used when BYPASS = 1.
0: C-tag: EtherType = 0x8100.
1: S-tag: EtherType = 0x88A8 or custom value.
PCP
13
3
The frame’s classified PCP. Used when BYPASS = 1.
DEI
12
1
The frame’s classified DEI. Used when BYPASS = 1.
VID
0
12
The frame’s classified VID. Used when BYPASS = 1.
Table 117 •
Node Processor Interface Registers
Register
Description
Replication
QSYS::EXT_CPU_CFG
Configuration of the NPI port number and
configuration of which CPU extraction queues
are redirected to the NPI.
None
SYS::PORT_MODE.INCL_XTR_HDR Enables insertion of extraction header.
Per port
SYS::PORT_MODE.INCL_INJ_HDR Configuration of NPI ingress mode.
Per port
Table 116 •
CPU Injection Header (continued)
Field
Bit
Width
Description



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