SSD1305Z datasheet(39/70 Pages) ETC1

39 / 70 page

SSD1305

Rev 1.9

P 39/70

May 2008

Solomon Systech

Table 9-2 : Read Command Table

Bit Pattern

Command

Description

D7D6D5D4D3D2D1D0

Status Register Read

D[7] :

Reserve

D[6] :

“1” for display OFF / “0” for display ON

D[5] :

Reserve

D[4] :

Reserve

D[3] :

Reserve

D[2] :

Reserve

D[1] :

Reserve

D[0] :

Reserve

Note

(1) Patterns other than those given in the Command Table are prohibited to enter the chip as a command; as unexpected

results can occur.

9.1

Data Read / Write

To read data from the GDDRAM, select HIGH for both the R/W# (WR#) pin and the D/C# pin for 6800-

series parallel mode and select LOW for the E (RD#) pin and HIGH for the D/C# pin for 8080-series parallel

mode. No data read is provided in serial mode operation.

In normal data read mode the GDDRAM column address pointer will be increased automatically by one after

each data read.

Also, a dummy read is required before the first data read.

To write data to the GDDRAM, select LOW for the R/W# (WR#) pin and HIGH for the D/C# pin for both

6800-series parallel mode and 8080-series parallel mode. The serial interface mode is always in write mode.

The GDDRAM column address pointer will be increased automatically by one after each data write.

Table 9-3 : Address increment table (Automatic)

D/C#

R/W# (WR#)

Comment

Address Increment

Write Command

Read Status

Write Data

Yes

Read Data

Yes (1)

Note

(1) If read-data command is issued in read-modify-write mode no address increase occurs.

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