July 2005

ASM5I9351

rev 0.2

2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer

3 of 13

Notice: The information in this document is subject to change without notice.

Pin Configuration

1

Pin #

Pin Name

I/O

Type

Description

8

PECL_CLK

I, PU

Analog

LVPECL reference clock input

.

9

PECL_CLK#

I, PU/PD

Analog

LVPECL reference clock input

. Weak pull-up to VDD/2.

30

TCLK

I, PD

LVCMOS

LVCMOS/LVTTL reference clock input

28

QA

O

LVCMOS

Clock output bank A

26

QB

O

LVCMOS

Clock output bank B

22, 24

QC(1:0)

O

LVCMOS

Clock output bank C

12, 14, 16, 18,

20

QD(4:0)

O

LVCMOS

Clock output bank D

2

FB_IN

I, PD

LVCMOS

Feedback clock input

. Connect to an output for normal

operation. This input should be at the same voltage rail as

input reference clock. See Table 1.

10

OE#

I, PD

LVCMOS

Output enable/disable input

. See Table 2.

31

PLL_EN

I, PU

LVCMOS

PLL enable/disable input

. See Table 2.

32

REF_SEL

I, PD

LVCMOS

Reference select input

. See Table 2.

3, 4, 5, 6

SEL(A:D)

I, PD

LVCMOS

Frequency select input, Bank (A:D)

. See Table 2.

27

VDDQB

Supply

VDD

2.5V or 3.3V Power supply for bank B output clock

2,3

23

VDDQC

Supply

VDD

2.5V or 3.3V Power supply for bank C output clocks

2,3

15, 19

VDDQD

Supply

VDD

2.5V or 3.3V Power supply for bank D output clocks

2,3

1

AVDD

Supply

VDD

2.5V or 3.3V Power supply for PLL

2,3

11

VDD

Supply

VDD

2.5V or 3.3V Power supply for core, inputs, and bank A

output clock

2,3

7

AVSS

Supply

Ground

Analog ground

13, 17, 21, 25,

29

VSS

Supply

Ground

Common ground

Note: 1 PU = Internal pull-up, PD = Internal pull-down.

2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins

their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.

3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output

power supply pins.