PMS132 datasheet(60/100 Pages) PADAUK

60 / 100 page

PMS132/PMS132B

8bit OTP MCU with 12-bit ADC

Page 60 of 100

PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020

Fig.19: Hardware diagram of IO buffer

Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output

mode (without Q1). The corresponding bits in registers padier / pbdier should be set to low to prevent leakage

current for those pins are selected to be analog function. When PMS132/PMS132B is put in power-down or

power-save mode, every pin can be used to wake-up system by toggling its state. Therefore, those pins

needed to wake-up system must be set to input mode and set the corresponding bits of registers padier and

pbdier to high. The same reason, padier.0 should be set high when PA0 is used as external interrupt pin,

pbdier.0 for PB0, padier.4 for PA4 and pbdier.5 for PB5.

5.13 Reset and LVR

5.13.1 Reset

There are many causes to reset the PMS132/PMS132B, once reset is asserted, most of all the registers in

PMS132/PMS132B will be set to default values, system should be restarted once abnormal cases happen,

or by jumping program counter to address 0x0. The data memory is in uncertain state when reset comes

from power-up and LVR; however, the content will be kept when reset comes from PRSTB pin or WDT

timeout.

5.13.2 LVR reset

By code option, there are many different levels of LVR for reset; usually, user selects LVR reset level to be

in conjunction with operating frequency and supply voltage.

(weak P -MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

padier.x or pbdier.x

Wakeup module

Interrupt module

(PA0,PB5,PB0,PA4)

(weak P -MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

padier.x or pbdier.x

Wakeup module

Interrupt module

(PA0,PB5,PB0,PA4)

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