PMS132 datasheet(37/100 Pages) PADAUK

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PMS132/PMS132B

8bit OTP MCU with 12-bit ADC

Page 37 of 100

PDK-DS-PMS132(B)-EN_V104 – Jun. 2, 2020

5.5. Comparator

One hardware comparator is built inside the PMS132/PMS132B; Fig.4 shows its hardware diagram. It can

compare signals between two pins or with either internal reference voltage Vinternal R or internal band-gap

reference voltage. The two signals to be compared, one is the plus input and the other one is the minus input.

For the minus input of comparator can be PA3, PA4, Internal band-gap 1.20 volt, PB6, PB7 or Vinternal R selected

by bit [3:1] of gpcc register, and the plus input of comparator can be PA4 or Vinternal R selected by bit 0 of gpcc

The comparator result can be selected through gpcs.7 to forcibly output to PA0 whatever input or output state.

It can be a direct output or sampled by Timer2 clock (TM2_CLK) which comes from Timer2 module. The output

polarity can be also inverted by setting gpcc.4 register, the comparator output can be used to request interrupt

service or read through gpcc.6.

Fig.4: Hardware diagram of comparator

gpcs.5=1

gpcs.5=0

gpcs.4=0

gpcs.4=1

16 stages

VDD

MUX

gpcs[3:0]

000

001

010

011

100

101

Timer 2

clock

TM2_CLK

gpcc.4

gpcc.5

gpcs.7

PA0

gpcc.6

gpcc[3:1]

PA3/CIN0-

PA4/CIN1-

Band-gap

PB6/CIN4-

PB7/CIN5-

PA4/CIN+

gpcc.0

Vinternal R

To request interrupt

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