TLC555CPWR datasheet(15/42 Pages) TI

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Time − 0.1 ms/div

Capacitor Voltage

Output Voltage

Input Voltage

Capacitance (nF)

0.01

0.1 0.2 0.5 1

2 3 5 710 20

50 100

1000

0.001

0.002

0.005

0.01

0.02

0.05

0.1

0.2

0.5

100

200

500

1000

2000

5000

10000

D006

1k:

10k:

100k:

1M:

10M:

Output

GND

OUT

CONT

RESET

DISCH

THRES

TRIG

Input

VDD

(5 V to 15 V)

TLC555

www.ti.com

SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019

Product Folder Links: TLC555

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Feature Description (continued)

Figure 9. Circuit for Monostable Operation

Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the

sequence ends only if TRIG is high for at least 1 µs before the end of the timing interval. When the trigger is

grounded, the comparator storage time can be as long as 1 µs, which limits the minimum monostable pulse width

to 1 µs. The output pulse duration is approximately tw = 1.1 × RAC. Figure 11 is a plot of the time constant for

various values of RA and C. The threshold levels and charge rates both are directly proportional to the supply

voltage, VDD. The timing interval is, therefore, independent of the supply voltage, so long as the supply voltage is

constant during the time interval.

Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges

capacitor C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low

as long as the reset pulse is low. To prevent false triggering, when RESET is not used it must be connected to

VDD.

RA = 9.1 kΩ

CL = 0.01 µF

See Figure 9

Figure 10. Typical Monostable Waveforms

Figure 11. Output Pulse Duration vs Capacitance

TLC555CPWR Datasheet(PDF) 15 Page - Texas Instruments

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