Time − 0.1 ms/div

Capacitor Voltage

Output Voltage

Input Voltage

Capacitance (nF)

0.1 0.2 0.5 1

2 3 5 710 20

50 100

1000

10000

0.01

0.02

0.05

0.1

0.2

0.5

1

2

5

10

20

50

100

200

500

1000

2000

D012

1k:

10k:

100k:

1M:

10M:

18

TLC555

SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019

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Copyright © 1983–2019, Texas Instruments Incorporated

Feature Description (continued)

Figure 15. Free-Running Frequency vs Timing Capacitance

7.3.3 Frequency Divider

By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency

divider. Figure 16 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during

the timing cycle.

C = 0.02 µF

See Figure 9

Figure 16. Divide-by-Three Circuit Waveforms