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TLC555CPWR Datasheet(PDF) 27 Page - Texas Instruments |
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TLC555CPWR Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 42 page  GND TRIG OUT RESET VDD DISCH THRES CONT C4 C3 R1 C1 C2 27 TLC555 www.ti.com SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019 Product Folder Links: TLC555 Submit Documentation Feedback Copyright © 1983–2019, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines Standard PCB rules apply to routing the TLC555. The 0.1-μF ceramic capacitor in parallel with a 1-μF electrolytic capacitor must be as close as possible to the TLC555. The capacitor used for the time delay must also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity. Figure 28 is the basic layout for various applications. • C1—based on time delay calculations • C2—0.01-μF bypass capacitor for control voltage pin • C3—0.1-μF bypass ceramic capacitor • C4—1-μF electrolytic bypass capacitor • R1—based on time-delay calculations 10.2 Layout Example Figure 28. Layout Example |
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