AT91SAM9261 datasheet(63/688 Pages) ATMEL

63 / 688 page

6062F–ATARM–05-Dec-06

AT91SAM9261 Preliminary

12.3.2

Test Environment

Figure 12-3 on page 63 shows a test environment example. Test vectors are sent and inter-

preted by the tester. In this example, the “board in test” is designed using a number of JTAG-

compliant devices. These devices can be connected to form a single scan chain.

Figure 12-3. Application Test Environment Example

12.4

Debug and Test Pin Description

Tester

JTAG

Interface

ICE/JTAG

Connector

AT91SAM9261-based Application Board In Test

AT91SAM9261

Test Adaptor

Chip 2

Chip n

Chip 1

Table 12-1.

Debug and Test Pin List

Pin Name

Function

Type

Active Level

Reset/Test

NRST

Microcontroller Reset

Input/Output

Low

TST

Test Mode Select

Input

High

ICE and JTAG

TCK

Test Clock

Input

TDI

Test Data In

Input

TDO

Test Data Out

Output

TMS

Test Mode Select

Input

NTRST

Test Reset Signal

Input

Low

RTCK

Returned Test Clock

Output

JTAGSEL

JTAG Selection

Input

ETM

TSYNC

Trace Synchronization Signal

Output

TCLK

Trace Clock

Output

TPS0 - TPS2

Trace ARM Pipeline Status

Output

TPK0 - TPK15

Trace Packet Port

Output

AT91SAM9261 Datasheet(PDF) 63 Page - ATMEL Corporation

AT91SAM9261 Datasheet(HTML) 63 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL