47L16 datasheet(15/40 Pages) MICROCHIP

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DS20005371C-page 15

47L04/47C04/47L16/47C16

2.4

Control Registers

To support device configuration features such as

software

write

protection,

well

software-controllable Store and Recall operations, the

47XXX features a set of Control registers that are

accessed using a different 4-bit op code than the op

code for the SRAM array (refer to Table 2-3 for op

code values).

Table 2-4 lists the available Control registers. The

STATUS register allows the user to configure the

47XXX. The COMMAND register is used to execute

special Software commands.

2.4.1

STATUS REGISTER

The STATUS register controls the software write

protection, enables/disables the Auto-Store function,

reports whether or not the array has been modified

since the last Store or Recall operation, and contains

the Hardware Store event flag.

There are several bits contained within the STATUS

•The AM bit indicates whether or not the SRAM

array has been written to since the last Store or

Recall operation. When set to a ‘0’, the SRAM

array matches the data in the EEPROM array.

When set to a ‘1’, the SRAM array no longer

matches the EEPROM array. The AM bit is set

whenever a data byte is written to the SRAM, and

is cleared after a Store or Recall operation is

completed. The AM bit must be a ‘1’ to enable the

Auto-Store

and

Hardware

Store

functions.

However, the Software Store command is always

enabled. The AM bit is volatile and is read-only.

•The BP bits control the SRAM array software

write protection. Table 2-5 lists the address

ranges that can be protected for each device. The

bits are nonvolatile.

•The ASE bit determines whether or not the

Auto-Store function is enabled. When set to a ‘1’,

the Auto-Store function is enabled and will exe-

cute automatically on power-down if the array has

been modified. When set to a ‘0’, the Auto-Store

function is disabled. The ASE bit is nonvolatile.

•The EVENT bit indicates whether or not an exter-

nal event has been detected on the HS pin. When

the HS pin is driven high, a STATUS register write

operation is automatically initiated following the

Hardware Store operation to set this bit to a ‘1’.

This bit can also be set and cleared through a

STATUS register Write command. The EVENT bit

is nonvolatile.

To store the nonvolatile bits in the STATUS register, a

write cycle occurs after a STATUS register write

operation, during which the 47XXX cannot be

accessed for TWC time after the Stop condition.

Note:

If an Auto-Store or Hardware Store is

triggered during a Control register read

or write operation, the operation is

aborted in order to execute the Store.

Note:

The COMMAND register is write-only.

TABLE 2-4:

CONTROL REGISTERS

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS

00h

—

BP2

BP1

BP0

ASE

EVENT

COMMAND

55h

CMD7

CMD6

CMD5

CMD4

CMD3

CMD2

CMD1

CMD0

Note:

If a capacitor is not connected to the

VCAP pin, then the VCAP pin must be

connected to VCC and the Auto-Store

feature must be disabled by writing the

ASE

bit to a ‘0’ to prevent data corrup-

tion in the EEPROM array when power

is lost.

Note:

The HS pin is ignored when VCAP is

below VTRIP, and during Store and

Recall operations. In these cases, the

EVENT

bit will not be written.

Note:

During a STATUS register write cycle, an

Auto-Store or Hardware Store can still be

triggered, but the Store operation will not

execute until the STATUS register write

cycle is complete (Figure 2-13). In this

situation, the new value of the ASE bit will

be used to determine if the Auto-Store is

executed.

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