ISO1640 datasheet(16/28 Pages) TI

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When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed by

RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the time-

constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before SDA2

reaches VCC2 potential.

8.4.2 Transmit Direction (Right Diagram of Figure 8-3 )

When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns

low it also causes the output of buffer B to turn low but at a higher 0.65 V level. This level cannot be observed

immediately as it is overwritten by the lower low-level of the master.

However, when the master releases SDA1, the voltage potential increases and first must pass the upper input

threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered

output level of VOL1 = 0.65 V, maintained by the receive path. When comparator C turns high, SDA2 is released

after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases

SDA1 to move toward VCC1 potential.

8.5 Device Functional Modes

Table 8-2 lists the ISO164x functional modes.

Table 8-2. Function Table (1)

POWER STATE

INPUT

OUTPUT

VCC1 < 2.3 V or VCC2 < 1.7 V

VCC1 > 2.9 V and VCC2 > 2.25

Z(2)

Undetermined

(1)

H = High Level; L = Low Level; Z = High Impedance or Float; X = Irrelevant

(2)

Invalid input condition as an I2C system requires that a pullup resistor to VCC is connected.

ISO1640

SLLSFC2 – OCTOBER 2020

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ISO1640 Datasheet(PDF) 16 Page - Texas Instruments