DAC53401 datasheet(21/53 Pages) TI

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8.3.3.2 NVM_CRC_ALARM_USER Bit

A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data is corrupt. During

this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be

written to or read from. To reset the alarm bits to 0, issue a software reset (see Section 8.3.6) command, or cycle

power to the DAC. Alternatively, cycle the power to reload the user-programmable NVM bits.

8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit

A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data is corrupt. During this

condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written

to or read from. To reset the alarm bits to 0, issue a software reset (see Section 8.3.6) command or cycle power

to the DAC.

8.3.4 Programmable Slew Rate

When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new

code following the slew rate and settling time specified in Section 7.5. The slew rate control feature allows the

user to control the rate at which the output voltage (V OUT) changes. When this feature is enabled (using

SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address

25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC)

using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting

(CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output

drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits

CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew

updates; CODE_STEP defines the amount by which the output value changes at each update. Table 8-2 and

Table 8-3 show different settings for CODE_STEP and SLEW_RATE.

When the slew rate control feature is used, the output changes happen at the programmed slew rate. This

configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or

DAC_DATA during the output slew.

Table 8-2. Code Step

AND NAME

CODE_STEP[2]

CODE_STEP[1]

CODE_STEP[0]

COMMENT

D1h, GENERAL_CONFIG

Code step size = 1 LSB

(default)

Code step size = 2 LSB

Code step size = 3 LSB

Code step size = 4 LSB

Code step size = 6 LSB

Code step size = 8 LSB

Code step size = 16 LSB

Code step size = 32 LSB

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