DRV8932PRGER datasheet(25/40 Pages) TI

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10 Layout

10.1 Layout Guidelines

The VM pin should be bypassed to PGND using a low-ESR ceramic bypass capacitor with a recommended

value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick

trace or ground plane connection to the device PGND pin.

The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an

electrolytic capacitor.

A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for

VM is recommended. Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16

V is recommended. Place this component as close to the pins as possible.

Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is

recommended. Place this bypassing capacitor as close to the pin as possible.

The thermal PAD must be connected to system ground.

10.1.1 Layout Example

Figure 10-1. HTSSOP Layout Example

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DRV8932

SLOSE58A – MAY 2020 – REVISED NOVEMBER 2020

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DRV8932PRGER Datasheet(PDF) 25 Page - Texas Instruments