SL3S4021 datasheet(6/30 Pages) NXP

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NXP Semiconductors

SL3S4011_4021

UCODE I²C

SL3S4011_4021

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Product data sheet

Rev. 3.5 — 18 September 2018

COMPANY PUBLIC

204935

6 / 30

The UCODE I2C communicates information by backscatter-modulating the amplitude

and/or phase of the RF carrier. Interrogators shall be capable of demodulating either

demodulation type.

The encoding format, selected in response to interrogator commands, is either FM0

baseband or Miller-modulated subaltern.

9.4 Data transfer to I2C interface

The UCODE I2C memory can be read/written similar to a standard I2C serial EEPROM

device. The address space is arranged in a linear manner. When performing a sequential

read, the address pointer is increased linearly from start of the EPC memory to the end of

the user memory.

At the end address of each bank, the address pointer jumps automatically to the first

address in the subsequent bank. In I2C write modes only even address values are

accepted, due to the word wise organization of the EEPROM.

Regarding arbitration between RF and I2C, see Section 12 "RF interface/I2C interface

arbitration").

Write operation:

• Write word

• Write block (2 words)

Read operation:

• current address read

• random address read

• sequential current read

• random sequential read

9.5 Supported commands

The UCODE I2C supports all mandatory EPCglobal V1.2.0 commands.

In addition, the UCODE I2C supports the following optional commands.

• Access

• BlockWrite (32 bit)

The UCODE I2C features the following custom commands described in more detail later:

• ChangeConfig

9.6 UCODE I2C memory

The UCODE I2C memory is implemented according to EPCglobal Gen2. It is organized

in four sections all accessible via both RF and I2C operation except the reserved memory

section which only accessible via RF:

Table 5. UCODE I2C memory sections

Name

Size

Bank

Reserved memory (32-bit ACCESS and 32-bit KILL password)

64 bit

00b

EPC (excluding 16 bit CRC-16 and 16-bit PC)

160 bit

01b

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