LTC3370 datasheet(16/22 Pages) AD

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LTC3315B

Rev. 0

For more information www.analog.com

GND

3315B F03

GROUND

PLANE ON

LAYER 2

R1, R3 KELVIN

TO GND ON

LAYER 4 TO VIAS

ON EXPOSED

PAD, PIN 13

VOUT2

CFF2

CFF1

VOUT1

COUT2

COUT1

CIN2

CIN1

VIN

APPLICATIONS INFORMATION

Figure 3. Recommended LTC3315B PCB Layout

pins 8 and 9 on the top layer. See the Analog Devices

Application Note, Application Notes for Thermally

Enhanced Leaded Plastic Packages for the proper size

and layout of the thermal vias and solder stencils.

2. Both of the input supply pins should have local decou-

pling capacitors with their grounded pins connecting

on the top layer to the ground plane around pin 8,

pin 9, and the exposed pad. These capacitors provide

the AC current to the internal power MOSFETs and

their drivers. Large, switched currents flow in these

capacitors and it is important to minimize inductance

from these capacitors by choosing a small case size

such as 0603 and placing them close to the VIN pins

of the LTC3315B. To further minimize inductance and

input noise, smaller 0201 capacitors can be placed

as close as possible to the LTC3315B directly on the

traces leading from VIN (Pin 7) and GND (Pin 8) and on

the traces leading from VIN (Pin 10) and GND (Pin 9)

minimal (if at all) increase in application footprint.

3. The switching power traces connecting SW1 and SW2

to their respective inductors should be minimized to

reduce radiated EMI and parasitic coupling. Due to

the large voltage swing on the switching nodes, high

input impedance sensitive nodes, such as the feedback

nodes, should be kept far away or shielded from the

switching nodes or poor performance could result.

4. The GND side of the switching regulator output capaci-

tors connects directly to the thermal ground plane

of the IC. Minimize the trace length from the output

capacitor to the inductor(s)/pin(s).

High Temperature Considerations

A thermal representation of the LTC3315B thermally

enhanced LQFN package is shown in Figure 4 with the

silicon die and thermal metrics identified. The current

source represents power loss PD on the die; node voltages

represent temperatures; electrical impedances represent

conductive thermal impedances θJCBOTTOM, θJCTOP, θVIA,

θCB, and convective thermal impedances θCA and θBA. The

junction temperature, TJ, is calculated from the ambient

temperature, TA, as:

TJ = TA + PD • θJA

(11)

where, neglecting the θJCTOP + θCA path:

θJA ≈θJCB +

θCB +θBA

⎛

⎝

⎞

⎠ !

θCB +θBA

+θVIA

⎛

⎝

⎞

⎠ (12)

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