LTC3370 datasheet(17/22 Pages) AD

17 / 22 page

LTC3315B

Rev. 0

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Figure 4. Multi-Layer PCB with Thermal Vias Acts as a Heat Sink

APPLICATIONS INFORMATION

θJCBOTTOM

θJCTOP

θCA

θCB

θVIA

θBA

PCB

LQFN

PCB

3315B F04

DIE

PACKAGE

SUBSTRATE

where θJCB = θJCBOTTOM = 10°C/W. The value of

θJA = 51°C/W reported in the Pin Configuration section

corresponds to JEDEC standard 2S2P test PCB, which

does not have good thermal vias, i.e., θVIA is relatively

high. Assuming, somewhat arbitrarily but not unreason-

ably, that θVIA ~ (θCB + θBA)/2, and back calculating it is

seen that (θCB + θBA)/2 = θVIA ≈ 60°C/W for such a board.

The importance of thermal vias becomes clear observing

that if the test PCB had low-thermal-resistance vias, the

θJA would have been reduced by up to 10°C/W, which is

an improvement of up to 20%. Similarly, having more

ground planes that are larger, uninterrupted and higher-

copper-weight improves θCB + θBA, which has a dominant

effect on θJA, given the low value of θJCBOTTOM of the

package. The maximum load current should be derated

as the ambient temperature approaches the maximum

junction rating. Power dissipation within the LTC3315B

is estimated by calculating the total power loss from an

efficiency measurement and subtracting the inductor loss.

LTC3370 Datasheet(PDF) 17 Page - Analog Devices