LM3075 datasheet(15/18 Pages) NSC

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MOSFET Selection (Continued)

input voltage and load current. The equation for the maxi-

mum allowable on resistance at room temperature for a

given FET package, is:

(16)

where T

J_MAX is the maximum allowed junction temperature

in the FET, T

A_MAX is the maximum ambient temperature,

RθJA is the junction-to-ambient thermal resistance of the

FET, and T

C is the temperature coefficient of the on resis-

tance which is typically in the range of 10,000ppm/˚C.

If the calculated R

dson_max is smaller than the lowest value

available, multiple FETs can be used in parallel. This effec-

tively reduces the I

MAX term in the above equation, thus

reducing R

dson. When using two FETs in parallel, multiply the

calculated R

dson_max by 4 to obtain the Rdson_max for each

FET. In the case of three FETs, multiply by 9.

Example:T

J_MAX = 100˚C, TA_MAX = 60˚C, R

θJA = 60˚C/W,

IN_MAX = 36V, VOUT = 5V, and IMAX =5A

(17)

If the selected FET has an R

dson value higher than 17.7

Ω,

then two FETs with an R

dson less than 30m

Ω can be used in

parallel. In this case, the temperature rise on each FET will

not go to T

J_MAX because each FET is now dissipating only

half of the total power.

TOP FET SELECTION

The output resistance for the top FET driver is 3.1

Ω (maxi-

mum). The bias voltage is developed by an external boot-

strap supply circuit, which is comprised of a diode and a

capacitor. Before selecting the top FET, it is recommended to

select the driving voltage for the bootstrap circuit first (see

more in the Bootstrap Component Selection section).

If VLIN5 is chosen to drive the bootstrap circuit, care must be

taken to ensure that the gate threshold voltage of the top

FET is less than 3V (maximum). The top FET starts to turn

on when the input voltage exceeds the threshold voltage of

the UVLO, which has a minimum threshold of 3.8V. In this

case, VLIN5 follows at approximately 3.8V also and thus the

bias voltage to the top FET driver is about 3V after the

bootstrap diode.

The top FET has two types of losses: switching loss and

conduction loss. The switching losses mainly consist of

crossover loss and bottom diode reverse recovery loss.

Since it is rather difficult to estimate the switching loss, a

general starting point is to allot 60% of the top FET thermal

capacity to switching losses. The best way to precisely de-

termine switching losses is through bench testing. The equa-

tion for calculating the on resistance of the top FET is thus:

(18)

Example: T

J_MAX = 100˚C, TA_MAX = 60˚C, R

θJA = 60˚C/W,

IN_MIN = 5.5V, VNOM = 5V, and IMAX = 5A.

(19)

When using FETs in parallel, the same guidelines apply to

the top FET as apply to the bottom FET.

BOOTSTRAP COMPONENT SELECTION

Selection of the bootstrap components can be done after top

FET and driving voltage are chosen. V

LIN5 or another supply

such as input may be used as the driving voltage. Once

chosen, the bootstrap components can be selected .

Typically a 0.1µF ceramic (X5R, X7R) works well.

Any suitably sized Schottky diode works well for the boot-

strap Diode. If excessive leakage current is seen, the a

larger bootstrap capacitance may be needed .

Loop Compensation

The purpose of loop compensation is to meet static and

dynamic performance requirements while maintaining stabil-

ity. Loop gain is usually checked to determine small-signal

performance. Loop gain is equal to the product of the

control-output transfer function and the output-control trans-

fer function (the compensation network transfer function).

Generally speaking, it is a good idea to have a loop gain

slope that is -20dB/decade from a very low frequency to well

beyond the crossover frequency. The crossover frequency

should not exceed one-fifth of the switching frequency. The

higher the bandwidth, the faster the load transient response

speed unless duty cycle saturates during a load transient.

Since the control-output transfer function usually has very

limited low frequency gain, it is a good idea to place a pole in

the compensation at zero frequency, so that the low fre-

quency gain is relatively large. A large DC gain means high

DC regulation accuracy (i.e. DC voltage changes little with

load or line variations). The rest of the compensation

scheme depends highly on the shape of the control-output

plot. As shown in Figure 6, the control-output transfer func-

tion consists of one pole (f

p), one zero (fz), and a double pole

at f

n (half the switching frequency). The following can be

done to create a -20dB/decade roll-off of the loop gain: Place

the first pole at 0Hz, the first zero at f

p, the second pole at fz,

and the second zero at f

n. The resulting output-control trans-

fer function is shown in Figure 7.

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