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TPS65921 Datasheet(PDF) 52 Page - Texas Instruments |
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TPS65921 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 66 page  SWCS048-025 OMAP host processor (LINK) ULPI_CLK ULPI_STP ULPI_DIR ULPI_NXT ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7 TXEN DAT SE0 TPS65921 USB PLL USB PWR USB CP ULPI USB 2.0 HS-OTG transceiver (PHY) Registers OTG VBUS D+ / RXD D– / TXD ID GND USB OTG connector VBAT VBAT.USB CVBAT.USB CVBUS CUSB3P1 CUSB.1P5 VBAT CUSB.1P3 CVBUS.PC CVBUS.IN TPS65921 SWCS048G – MARCH 2010 – REVISED SEPTEMBER 2014 www.ti.com Figure 5-14 shows the USB system application schematic. Figure 5-14. USB System Application Schematic 5.5.7 PHY The PHY is the physical signaling layer of the USB 2.0. It contains all the drivers and receivers required for physical data and protocol signaling on the DP and DM lines. The PHY interfaces to the USB controller through a standard digital interface called the universal transceiver macro cell interface (UTMI). The transmitters and receivers inside the PHY are classified into two main classes: • The FS and LS transceivers. These are the legacy USB1.x transceivers. • The HS transceivers To bias the transistors and run the logic, the PHY also contains reference generation circuitry consisting of: • A DPLL, which does a frequency multiplication to achieve the 480-MHz low-jitter lock necessary for USB, and also the clock required for the switched capacitor resistance block. • A switched capacitor resistance block used to replicate an external resistor on chip. Built-in pullup and pulldown resistors are used as part of the protocol signaling. Apart from this, the PHY also contains circuitry that protects it from an accidental 5 V short on the DP and DM lines. 52 Detailed Description Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS65921 |
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