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Communication Interface

I²C Communication

Application Note

• PUBLIC

AN000710

• v1-00 • 2020-Jul-21

12

│ 7

(3)

automatically done if the device does not stretch the low phase of SCL. If such a device does stretch the low phase of

(4)

In the Fast-mode plus, fall time is specified the same for both output stage and bus timings. If series resistors are used,

this has to be considered for bus timing.

2.3

I²C Communication

Figure 6 :

I²C Communication

2.3.1

Data Transmission

The state of the data line represents valid data when, after START condition, the data line is stable for

the duration of the HIGH period of the clock signal. The data on the line must be changed during the

LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

information is transferred byte-wise and each receiver acknowledges with a ninth bit.

2.3.2

Acknowledge

The receiving device is obliged to generate an acknowledge after the reception of each byte. The

master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such

a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse.

Of course, setup and hold times must be taken into account. A master must signal an end of READ

access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of

the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the

STOP condition.