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LTC2913 Datasheet(PDF) 18 Page - Analog Devices

Part # LTC2913
Description  100V UV/OV and Reverse Protection Controller with Bidirectional Circuit Breaker
PDF  22 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTC2913 Datasheet(HTML) 18 Page - Analog Devices

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LTC4368
18
Rev. B
For more information www.analog.com
Transients During OV Fault
The circuit of Figure 19 is used to illustrate transients
commonly encountered during an overvoltage condition.
The nominal input supply is 48V and it has an overvoltage
threshold of 60V. The parasitic inductance is that of a 1
foot wire (roughly 300nH). Figure 20 shows the wave-
forms during on overvoltage condition at VIN. These tran-
sients depend on the parasitic inductance and resistance
of the wire along with the capacitance at the VIN node.
D1 is an optional power clamp (TVS, TransZorb) recom-
mended for applications where the DC input voltage can
exceed 24V and with large VIN parasitic inductance. No
clamp was used to capture the waveforms of Figure 20. In
order to maintain reverse supply protection, D1 must be
a bidirectional clamp with appropriate voltage and power
ratings.
Layout Considerations
The trace length between the VIN pin and the drain of the
external MOSFET should be minimized, as well as the
trace length between the GATE pin of the LTC4368 and
the gates of the external MOSFETs. The SENSE and VOUT
pins must be connected with traces that tie directly and
solely to the sense resistor.
Place the bypass capacitors at VOUT as close as possible
to the external MOSFET. Use high frequency ceramic
capacitors in addition to bulk capacitors to mitigate hot
swap ringing. Place the high frequency capacitors closest
to the MOSFET. Note that bulk capacitors mitigate ringing
by virtue of their ESR. Ceramic capacitors have low ESR
and can thus ring near their resonant frequency. The trace
length of the GATE pin should be kept as small as pos-
sible, and the number of components connected to the
GATE pin should also be minimized.
The SOA of the external MOSFET might require the board
to have a minimum total area as well as a minimum amount
of trace volume connected to the drain and source pins.
APPLICATIONS INFORMATION
Figure 19. OV Fault with Large VIN Inductance
VIN
48V
FDS3992
100V DUAL
R4
100k
COUT
100µF
48
R2
2430k
R1
20.5k
+
D1
RETRY
4368 F19
VOUT
FAULT
LTC4368-2
SENSE
CRETRY
0.22µF
VIN
UV
OV
SHDN
GATE
GND
RSENSE
0.02
CGATE
3.3nF
INRUSH
CONTROL: ~1A
RGATE
22k
1200ms COOLDOWN
AFTER FORWARD
OC FAULT
300nH
(12 INCH WIRE LENGTH)
OV = 60V
Figure 20. Transients During 0V Fault when
No TransZorb (TVS) Is Used
400ns/DIV
VIN
20V/DIV
VOUT
20V/DIV
GATE
IIN
2A/DIV
4368 F20
60V
60V
0A



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