DAC61402 datasheet(32/52 Pages) TI

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7.5.3 Frame Error Checking

If the device is used in a noisy environment, error checking can be used to check the integrity of SPI data

communication between the device and the host processor. This feature is enabled by setting the CRC-EN bit.

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (that is, 100000111).

When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are

appended with an 8-bit CRC polynomial by the host processor before feeding the data to the device. In all serial

interface readback operations, the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.

Table 7-4. Error Checking Serial Interface Access Cycle

BIT

FIELD

DESCRIPTION

Identifies the communication as a read or write command to the address

R/W = 0 sets a write operation.

R/W = 1 sets a read operation.

CRC-ERROR

Reserved bit. Set to zero.

29-24

A[5:0]

write operation.

23-8

DI[15:0]

Data cycle bits.

If a write command, the data cycle bits are the values to be written to the

If a read command, the data cycle bits are don't care values.

7-0

CRC

8-bit CRC polynomial.

The device decodes the 32-bit access cycle to compute the CRC remainder on SYNC rising edges. If no error

exists, the CRC remainder is zero and data are accepted by the device.

A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a

second access cycle can be issued to determine the error checking results (CRC-ERROR bit) on the SDO pin.

If there is a CRC error, the CRC-ALM bit of the status register is set to 1. The FAULT pin can be configured to

monitor a CRC error by setting the CRCALM-EN bit.

Table 7-5. Write Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 0).

CRC-ERROR

Returns a 1 when a CRC error is detected; otherwise, returns a 0.

29-24

A[5:0]

Echo address from previous access cycle.

23-8

DO[15:0]

Echo data from previous access cycle.

7-0

CRC

Calculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The

error check result (CRC-ERROR bit) from the read command is output on the SDO pin.

As in the case of a write operation failing the CRC check, the CRC-ALM bit of the status register is set to 1, and

the ALMOUT pin, if configured for CRC alerts, is set low.

Table 7-6. Read Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 1).

CRC-ERROR

Returns a 1 when a CRC error is detected; otherwise, returns a 0.

29-24

A[5:0]

Echo address from previous access cycle.

23-8

DO[15:0]

Readback data requested on previous access cycle.

7-0

CRC

Calculated CRC value of bits 31:8.

DAC61402

SLASEH3 – NOVEMBER 2020

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