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DAC61402 Datasheet(PDF) 13 Page - Texas Instruments

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Part # DAC61402
Description  DAC61402 Dual, 12-Bit, High-Voltage-Output DAC With Internal Reference
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC61402 Datasheet(HTML) 13 Page - Texas Instruments

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6.6 Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 1.7 V ≤ IOVDD < 2.7 V
PARAMETER
MIN
NOM
MAX
UNIT
fSCLK
SCLK frequency
25
MHz
tSCLKHIGH
SCLK high time
20
ns
tSCLKLOW
SCLK low time
20
ns
tSDIS
SDIN setup
10
ns
tSDIH
SDIN hold
10
ns
tCSS
SYNC to SCLK falling edge setup
30
ns
tCSH
SCLK falling edge to SYNC rising edge
10
ns
tCSHIGH
SYNC high time
50
ns
tDACWAIT
Sequential DAC update wait time
2.4
µs
tBCASTWAIT
Broadcast DAC update wait time
4
µs
tLDACAL
SYNC rising edge to LDAC falling edge
80
ns
tLDACW
LDAC low time
20
ns
tCLRW
CLR low time
20
ns
tRSTW
RST low time
20
ns
6.7 Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
all specifications at TA = –40°C to +125°C, input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed
from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, 2.7 V ≤ IOVDD ≤ 5.5 V
PARAMETER
MIN
NOM
MAX
UNIT
fSCLK
SCLK frequency
50
MHz
tSCLKHIGH
SCLK high time
10
ns
tSCLKLOW
SCLK low time
10
ns
tSDIS
SDIN setup
5
ns
tSDIH
SDIN hold
5
ns
tCSS
SYNC to SCLK falling edge setup
15
ns
tCSH
SCLK falling edge to SYNC rising edge
5
ns
tCSHIGH
SYNC high time
25
ns
tDACWAIT
Sequential DAC update wait time
2.4
µs
tBCASTWAIT
Broadcast DAC update wait time
4
µs
tLDACAL
SYNC rising edge to LDAC falling edge
40
ns
tLDACW
LDAC low time
20
ns
tCLRW
CLR low time
20
ns
tRSTW
RST low time
20
ns
www.ti.com
DAC61402
SLASEH3 – NOVEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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