LM27241 datasheet(13/27 Pages) NSC

13 / 27 page

Operation Descriptions (Continued)

As mentioned in the section ‘Forced-PWM Mode and Pulse-

skip Mode’ under startup, since the current is high until the

output capacitors have charged up, there will be no observ-

able difference in the shape of the ramp-up of the output rail

in either SKIP mode or FPWM mode. The design has thus

forced the startup waveforms to be identical irrespective of

whether the FPWM mode or the SKIP mode has been

selected.

SHUTDOWN/SOFT-SHUTDOWN

When the EN pin is driven low, the LM27241 initiates shut-

down by turning OFF both upper and lower FETs completely

(this occurs irrespective of FPWM or SKIP modes). See

Figure 6 for a typical shutdown plot and note that the LDRV

goes to zero (and stays there). Though not displayed, Power

Good also goes low within less than 100ns of the EN pin

going low (t

SD, see Electrical Characteristics table). There-

fore in this case, the controller is NOT waiting for the output

to actually fall out of the Power Good window before it

signals Power Not Good. When the part is shutdown with a

constant current load, the time taken for the output to decay

may be calculated using the equation V/t = i/C. For example,

there is a constant current 2A load applied at the output and

the charge stored on the output capacitor continues to dis-

charge into the load. From V/t = i/C = 2A/330µF, it can be

seen that the output voltage (say 1V) will fall to zero in about

165µs.

POWER GOOD/NOT GOOD SIGNALING

PGOOD is an open-drain output pin with an external pull-up

resistor connected to 5V. It goes high (non-conducting) when

the output is within the regulation band as determined by the

Power Good window detector stage on the feedback pin

(see Block Diagram). PGOOD goes low (conducting) when

the output falls out of this window. This signal is referred to

as Power Not Good here. A glitch filter of 7µs filters out

noise, and helps to prevent spurious PGOOD responses. So

Power Not Good is not asserted until 7µs after the output has

fallen out of the Power Good window (see

∆t

PG_NOK in

Electrical Characteristics table). With the feedback pin volt-

age rising towards regulation value, there is a 20µs delay

between the output being in regulation and the signaling of

Power Good (see

∆t

PG_OK

in Electrical Characteristics

table). Power Not Good is signaled within 100ns of the

Enable pin being pulled low (see

∆t

SD in Electrical Charac-

teristics table), irrespective of the fact that the output could

still be in regulation. The Soft-start capacitor is also then

discharged as explained earlier.

FAULT AND RECOVERY

If the output falls outside the Power Good window, the

response is a ‘Power Not Good’ signal. The FET drive sig-

nals are not affected. But under a fault condition assertion,

LDRV goes high immediately turning the low-side FET ON

and discharging the output capacitors. The inductor current

will then invariably slew momentarily negative (passing from

drain to source of low-side FET), before it settles down to

zero. A fault will be detected when the output falls below the

Under-voltage threshold, or rises above the Over-voltage

threshold. From its detection to assertion, there is a 7µs

delay to help to prevent spurious responses. A fault condition

is also asserted during a loss of the VIN rail or the VDD rail.

If the Enable pin is brought low prior to this fault, a soft

shutdown will occur. To recover from a fault, either of the

following options is available:

1) Enable pin is toggled: i.e. taken low (below 0.8V), then

high again (2V to 5V). This must be done with VDD between

4.5V to 5V and VIN within normal range (5.5V to 28V).

2) VDD is brought below 1.0V and then brought back up

between 4.5V to 5V. This must be done with the Enable pin

held high (2V to 5V) and VIN within normal range (5.5V to

28V).

Recovery will initiate a Soft-start sequence (see description

under section ‘Soft-start’ above).

VIN POWER-OFF (UVLO)

The LM27241 has an internal comparator that monitors VIN.

If VIN falls to approximately 4.4V, switching ceases and both

top and bottom FETs are turned OFF. ‘Power Not Good’ has

meanwhile already been signaled and a fault condition as-

serted shortly thereafter.

20120114

CH1: LDRV, CH2: Vo, CH3: SW, CH4: IL (1A/div)

Output 1V @ 2A, VIN = 10V, FPWM/SKIP, L = 10µH, f = 300kHz, COUT =

330µF

FIGURE 6. Shutdown

20120191

FIGURE 7. Startup Power OK

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