AD8253 datasheet(18/34 Pages) AD

18 / 34 page

LTC6373

Rev. 0

For more information www.analog.com

Functional Description

The LTC6373 is a monolithic instrumentation amplifier

based on the classic 3-op-amp topology, as shown in

the Block Diagram of Figure 1. A parallel interface allows

users to digitally program gains to one of the seven avail-

able settings (G = 0.25, 0.5, 1, 2, 4, 8, and 16V/V) while

the 8th state puts the part in shutdown mode (which

reduces the current drawn from the supplies to 220µA).

Gain control is achieved by switching resistors in an

internal, precision resistor array (as shown in Figure 1).

Although the LTC6373 has a voltage feedback topology,

the gain-bandwidth product increases at higher gain set-

tings because each gain has its own frequency compensa-

tion, resulting in increased bandwidth at higher gains and

minimum phase variation across all gains.

The LTC6373 is optimized to convert a fully differential or

single-ended input signal to a low impedance, balanced

differential output suitable for driving high performance,

analog-to-digital converters (ADCs). The balanced differ-

ential nature of the amplifier provides even-order har-

monic distortion cancellation, and low susceptibility to

common mode noise (like power supply noise). Load

capacitances above 50pF to ground or 25pF differentially

should be decoupled with 10Ω to 50Ω of series resistance

from each output to prevent oscillation or ringing.

Overall, the LTC6373 simplifies signal chain design by

offering:

• High impedance buffering (due to using CMOS

technology and the resulting pA input bias current)

• Signal amplification (G>1) and attenuation (G<1)

together in one socket at nearly the same bandwidth

• Digital gain programming (which enables changing

gain settings easily and rapidly)

• Superior matching specs (due to trimmed, precision

internal resistors)

• The ability to drive ADCs directly (due to attributes

such as fully differential outputs, good DC precision,

low noise, low distortion, and high bandwidth)

• Level shifting (achieved by using VOCM pin to inde-

pendently adjust the output common mode voltage to

match it to the desired input level of the next stage of

the signal chain).

The LTC6373 accommodates all the above features in a

small 12-lead 4mm × 4mm DFN (LFCSP) package, mak-

ing it an excellent solution for applications where size and

packing density are important considerations.

Gain Selection

The gain of the LTC6373 can be programmed to its desired

setting using a digital interface consisting of a digital ref-

erence pin DGND and three parallel gain programming

pins A2, A1, and A0. The logic threshold for A2/A1/A0

pins is specified with respect to the voltage on the DGND

pin. Any voltage between DGND and DGND + 0.6V on A2

or A1 or A0 pins will generate a logic low (L) state for that

pin; any voltage between DGND + 1.5V and V+ on A2 or

A1 or A0 pins will generate a logic high (H) state for that

pin. The gain for the LTC6373 is programmed according

to the truth table below:

Table 1. Gain Selection Table for LTC6373

G = GAIN SETTING (V/V)

0.5

0.25

Shutdown

The permissible voltage range for DGND is between V– and

V+ – 2.5V. However, typically DGND is tied to ground (0V)

and A2/A1/A0 pins can be connected to 0V or 5V to gener-

ate logic low (L) and logic high (H) states, respectively.

If the DGND pin is left floating, an internal resistor divider

creates a default voltage approximately halfway between

V+ and V–. Additionally, if A2 or A1 or A0 pins are left

floating, internal resistors pull the voltage on each of these

pins close to the DGND pin, resulting in a default logic low

(L) state for that programming pin. As a result, if A2 and

A1 and A0 pins are left floating all at the same time, the

LTC6373 will have a gain setting of G = 16. When these

pins are left open, care should be taken to control leakage

currents at these pins to prevent inadvertently putting the

LTC6373 into an undesired gain setting.

APPLICATIONS INFORMATION

AD8253 Datasheet(PDF) 18 Page - Analog Devices

AD8253 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL