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AD8253 Datasheet(PDF) 25 Page - Analog Devices |
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AD8253 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 34 page ![]() LTC6373 25 Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION impedance mismatches internally to the IC. Additionally, the CAP pin should be bypassed to the ground plane with a high quality 180pF ceramic capacitor to ensure proper operation of LTC6373 across its different gain settings. To prevent coupling noise onto LTC6373, shield fast switching digital signals where they are in proximity of analog signals on the board. Driving High Precision ADCs The LTC6373 makes an excellent PGIA for use in data acquisition systems. Attributes such as fully differen- tial outputs, good DC precision, low noise, low distor- tion, and high bandwidth enable LTC6373 to drive ADCs directly in many signal conditioning applications. The recommended list of precision SAR ADCs for use with the LTC6373 is shown in Table 3. The circuit in Figure 8 shows an example of the LTC6373 driving a precision ADC such as the AD4020 (a 20-bit, 1.8Msps, SAR ADC) or AD7134 (a 24-bit, 1.5Msps, Continuous-Time, ∑-∆ ADC). The LTC6373 is DC-coupled on the input and the output, which eliminates the need for a transformer to drive the ADC. The LTC6373 gain is programmed to its desired set- ting using A2/A1/A0 pins, as previously described in the Gain Selection section of this data sheet. In the example of Figure 8, the LTC6373 is being used in a differential input to differential output configuration with dual sup- plies of ±15V. It can also be used in a single-ended input to differential output configuration. The VOCM pin is biased to VREF/2 (which is provided directly by the ADC in some products). This achieves level shifting of the outputs of the LTC6373 to match the desired input common mode of the ADC. In Figure 8, each of the LTC6373 outputs swings between 0V and VREF (opposite in phase), thus providing 2VREF peak-to-peak differential signal to the ADC inputs. In some cases, an RC network between the LTC6373 outputs and the ADC inputs is required providing a single-pole, low-pass filter to help reduce nonlinear charge kickback due to ADC input switching as well as limiting the broadband noise. Table 3. Recommended SAR ADCs Resolution (Bits) Product Max Throughput (Msps) Power @ Max Throughput (mW) Typical SNR (dB) 20 AD4020 1.8 15 100.5 LTC2378-20 1 21 104 18 AD4003 2 16 100.5 LTC2379-18 1.6 18 101.2 16 AD4001 2 16 96.2 LTC2380-16 2 19 96.2 |
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