ADC3663 datasheet(11/71 Pages) TI

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6.8 Timing Requirements (continued)

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to

TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tCD

DCLK rising edge to output data

delay,

2-wire SLVDS, 14-bit

Fout = 65 MSPS, DA/B0,1 = 455 MBPS

0.1

Fout = 80 MSPS, DA/B0,1 = 560 MBPS

0.1

Fout = 125 MSPS, DA/B0,1 = 875 MBPS

-0.2

0.1

DCLK rising edge to output data

delay,

1-wire SLVDS, 14-bit

Fout = 65 MSPS, DA/B0 = 910 MBPS

0.1

DCLK rising edge to output data

delay,

1-wire SLVDS, 16-bit

Fout = 10 MSPS, DA/B0 = 160 MBPS

0.1

Fout = 25 MSPS, DA/B0 = 400 MBPS

0.1

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

-0.6

0.1

DCLK rising edge to output data

delay,

1/2-wire SLVDS, 16-bit

Fout = 5 MSPS, DA0 = 160 MBPS

0.1

Fout = 10 MSPS, DA0 = 320 MBPS

0.1

Fout = 25 MSPS, DA0 = 800 MBPS

0.1

tDV

Data valid, 2-wire SLVDS, 14-bit

Fout = 65 MSPS, DA/B0,1 = 455 MBPS

1.8

1.9

Fout = 80 MSPS, DA/B0,1 = 560 MBPS

1.4

1.5

Fout = 125 MSPS, DA/B0,1 = 875 MBPS

0.6

0.8

Data valid, 1-wire SLVDS, 14-bit

Fout = 65 MSPS, DA/B0 = 910 MBPS

0.6

0.8

Data valid, 1-wire SLVDS, 16-bit

Fout = 10 MSPS, DA/B0 = 160 MBPS

5.7

5.8

Fout = 25 MSPS, DA/B0 = 400 MBPS

2.0

2.1

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

0.5

0.6

Data valid, 1/2-wire SLVDS, 16-bit

Fout = 5 MSPS, DA0 = 160 MBPS

5.7

5.8

Fout = 10 MSPS, DA0 = 320 MBPS

2.7

2.8

Fout = 25 MSPS, DA0 = 800 MBPS

0.8

0.9

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

fCLK,SCLK

Serial clock frequency

MHz

tS,SEN

SEN falling edge to SCLK rising edge

tH,SEN

SCLK rising edge to SEN rising edge

tS,SDIO

SDIO setup time from rising edge of SCLK

tH,SDIO

SDIO hold time from rising edge of SCLK

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

tOZD

Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from

tri-state to valid data

3.9

10.8

tODZ

Delay from SEN rising edge for SDIO transition from valid data to tri-state

3.4

tOD

Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid

3.9

10.8

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ADC3664

SBAS888 – DECEMBER 2020

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