ADC3663 datasheet(24/71 Pages) TI

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8.3.2 Clock Input

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications (Figure 8-8 and Figure

8-9). For less jitter sensitive applications, the ADC3664 provides the option to operate with single ended

signaling which saves additional power consumption.

Figure 8-8. AC Performance vs Clock Amplitude

for FIN = 5 MHz

Figure 8-9. AC Performance vs Clock Amplitude

for FIN = 70 MHz

8.3.2.1 Single Ended vs Differential Clock Input

The ADC3664 can be operated using a differential or a single ended clock input where the single ended clock

consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently

the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC3664 provides internal

biasing for that use case.

• Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with

the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC

coupled around a 0.9V center. The unused input needs to be AC coupled to ground.

VCM

0.9V

CLKP

CLKM

5kO

CLKP

CLKM

0.9V

1.8V

Figure 8-10. External and internal connection using differential (left) and single ended (right) clock input

ADC3664

SBAS888 – DECEMBER 2020

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ADC3663 Datasheet(PDF) 24 Page - Texas Instruments