DRV8955PRGER datasheet(21/45 Pages) TI

21 / 45 page

operation resumes (motor-driver operation and nFAULT released) when the VM undervoltage condition is

removed.

7.3.6.2 VCP Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin falls below the CPUV voltage, all the outputs are disabled, and the

nFAULT pin is driven low. The charge pump remains active during this condition. Normal operation resumes

(motor-driver operation and nFAULT released) when the VCP undervoltage condition is removed.

7.3.6.3 Overcurrent Protection (OCP)

An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this

current limit persists for longer than the tOCP time, the half-bridge in which OCP is detected is disabled and the

nFAULT pin is driven low. The charge pump remains active during this condition. Once the OCP condition is

removed, normal operation resumes after applying an nSLEEP reset pulse or a power cycling.

7.3.6.4 Thermal Shutdown (OTSD)

If the die temperature exceeds the thermal shutdown limit (TOTSD) all MOSFETs in the H-bridge are disabled,

and the nFAULT pin is driven low. After the junction temperature falls below the overtemperature threshold limit

minus the hysteresis (TOTSD – THYS_OTSD), normal operation resumes after applying an nSLEEP reset pulse or a

power cycling.

Fault Condition Summary

Table 7-7. Fault Condition Summary

FAULT

CONDITION

ERROR

REPORT

HALF-

BRIDGE

CHARGE

PUMP

LOGIC

RECOVERY

VM undervoltage

(UVLO)

VM < VUVLO

nFAULT

All Disabled

Disabled

Reset

(VDVDD < 3.9

Automatic: VM > VUVLO

CP undervoltage

(CPUV)

VCP < VCPUV

nFAULT

All Disabled

Operating

VCP > VCPUV

Overcurrent (OCP)

IOUT > IOCP

nFAULT

Half-bridge

with OCP is

Disabled

Operating

Latched

Thermal Shutdown

(OTSD)

TJ > TTSD

nFAULT

All Disabled

Disabled

Operating

Latched

7.4 Device Functional Modes

7.4.1 Sleep Mode (nSLEEP = 0)

The state of the device is managed by the nSLEEP pin. When the nSLEEP pin is low, the device enters a low-

power sleep mode. In sleep mode, all the internal MOSFETs are disabled and the charge pump is disabled. The

tSLEEP time must elapse after a falling edge on the nSLEEP pin before the device enters sleep mode. The device

is brought out of sleep automatically if the nSLEEP pin is brought high. The tWAKE time must elapse before the

device is ready for inputs.

7.4.2 Operating Mode (nSLEEP = 1)

When the nSLEEP pin is high, and VM > UVLO, the device enters the active mode. The tWAKE time must elapse

before the device is ready for inputs.

7.4.3 nSLEEP Reset Pulse

A latched fault can be cleared through a quick nSLEEP pulse. This pulse width must be greater than 20 µs and

shorter than 40 µs. If nSLEEP is low for longer than 40 µs, but less than 120 µs, the faults are cleared and the

device may or may not shutdown, as shown in the timing diagram (see Figure 7-14). This reset pulse does not

affect the status of the charge pump or other functional blocks.

www.ti.com

DRV8955

SLOSE71 – APRIL 2020 – REVISED DECEMBER 2020

Submit Document Feedback

Product Folder Links: DRV8955

DRV8955PRGER Datasheet(PDF) 21 Page - Texas Instruments

DRV8955PRGER Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL