RA6M3 datasheet(60/116 Pages) RENESAS

60 / 116 page

R01DS0358EJ0110 Rev.1.10

Page 60 of 116

Dec 25, 2020

RA6M3 Group

2. Electrical Characteristics

Note:

tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.

Note 1.

This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not

guaranteed.

Note 2.

The load is 30 pF.

Note 3.

Constraints on input cycle:

When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.

When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Figure 2.34

I/O ports input timing

Figure 2.35

POEG input trigger timing

GPT32

Input capture pulse width

Single edge

tGTICW

1.5

tPDcyc

Figure 2.36

Dual edge

2.5

GTIOCxY output skew

(x = 0 to 7, Y= A or B)

Middle drive buffer

tGTISK*1 -4

Figure 2.37

High drive buffer

GTIOCxY output skew

(x = 8 to 13, Y = A or B)

Middle drive buffer

High drive buffer

GTIOCxY output skew

(x = 0 to 13, Y = A or B)

Middle drive buffer

High drive buffer

OPS output skew

GTOUUP, GTOULO, GTOVUP,

GTOVLO, GTOWUP, GTOWLO

tGTOSK

-5

Figure 2.38

GPT(PWM

Delay

Generation

Circuit)

GTIOCxY_Z output skew

(x = 0 to 3, Y = A or B, Z = A)

tHRSK*2 -2.0

Figure 2.39

AGT

AGTIO, AGTEE input cycle

tACYC*3 100

Figure 2.40

AGTIO, AGTEE input high width, low width

tACKWH,

tACKWL

AGTIO, AGTO, AGTOA, AGTOB output cycle

tACYC2

62.5

ADC12

ADC12 trigger input pulse width

tTRGW

1.5

tPcyc

Figure 2.41

KINT

KRn (n = 00 to 07) pulse width

tKR

250

Figure 2.42

Table 2.19

I/O ports, POEG, GPT32, AGT, KINT, and ADC12 trigger timing (2 of 2)

GPT32 Conditions:

High drive output is selected in the port drive capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol Min

Max

Unit

Test

conditions

Port

tPRW

POEG input trigger

tPOEW

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