3.3V Single-Piece 1Mb Nonvolatile SRAM

with Clock

14

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When the RTC register values match alarm register set-

tings, the alarm flag (AF) is set to a 1. If AE is also a 1,

the alarm condition activates the IRQ/FT output. When

CS is active, the IRQ/FT signal can be cleared by hold-

ing either OE or WE active (see Figure 1). The flag does

not change state until the end of the read/write cycle

and after the IRQ/FT signal has deasserted. To avoid

inadvertently clearing the IRQ/FT signal while preparing

for subsequent write/read cycles at other register

address (see Figure 2).

The IRQ/FT output can also be activated during battery

backup mode. The IRQ/FT goes low if an alarm occurs

and both AE and ABE are set to 1. The AE and ABE

bits are reset to 0 during the power-up transition, but an

alarm generated during power-up will set AF to a 1.

Therefore, the AF bit can be read after system power-

up to determine if an alarm was generated during the

power-up sequence. Figure 3 illustrates alarm timing

during battery backup mode and power-up states.

Table 3. Alarm Mask Bits

AM4

AM3

AM2

AM1

ALARM RATE

111

1

Once per second

111

0

When seconds match

110

0

When minutes and seconds match

100

0

When hours, minutes, and seconds match

000

0

When date, hours, minutes, and seconds match

CE

WE OR OE

CS

A0–A3

IRQ/FT

ADDRESS 0h

HIGH IMPEDANCE

Figure 1. Clearing Active IRQ Waveforms