M62384FP

REJ03F0077-0200 Rev.2.00 Mar 25, 2008

Page 2 of 7

Block Diagram

GND

SLD

SCK

8

SDI

CS0

CS1

Vref

Ao1

Ao2

Ao3

Ao4

VSS

RST

1

2

36

7

16

15

10

12-bit shift register

Power-on

reset

4

5

14

13

12

11

9

Channel

decoder

8-bit latch

8-bit D-A

8-bit D-A

8-bit D-A

8-bit D-A

8-bit latch

8-bit latch

8-bit latch

Pin Functions

Pin No.

Symbol

Function

1, 8

GND

Analog GND: analog circuit GND

(D-A converter lower reference voltage)

2

Ao1

3

Ao2

6

Ao3

7

Ao4

D-A converter output pins (ch1 to ch4): full-swing buffer output

Output voltage: Ao (00)h = 0V, Ao (FF)h = 255/256

× VREF

4

Vcc

Analog power supply (3 V to 5 V)

Must rise simultaneously with VDD or after VDD rise.

5

Vref

D-A converter upper reference voltage input pin

9

Vss

Digital GND

10

SLD

Serial load signal input pin (Schmitt trigger input: with input hysteresis)

When SLD is high, data is loaded from shift register into 8-bit latch corresponding to

address.

11

SDI

Serial data input pin (TTL input in case of 5 V power supply)

Inputs serial data with a 12-bit data length (MSB-first).

12

SCK

Serial clock signal input pin (Schmitt trigger input: with input hysteresis)

At rising edge, data is read into shift register one bit at a time.

13

VDD

Digital power supply pin (3 V to 5 V)

When power supply rises, D-A output is reset (0 V output: power-on reset).

14

RST

Forced reset pin (TTL input in case of 5 V power supply)

L: D-A output (AO1 to 4) = Fixed setting of 0 V

H: Reset release (power-on reset operation)

15

CS0

16

CS1

Chip select pins (TTL input in case of 5 V power supply)

Access possible only when chip select data (D11, D10) and pin (CS1, CS0) logic

match.