ADPA7004CHIPS

Data Sheet

Rev. 0 | Page 6 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RFOUT

RFIN

1

8

16

15

14

12

11

10

9

13

2

3

4

6

7

5

ADPA7004CHIPS

TOP VIEW

(Not to Scale)

Figure 2. Pad Configuration

Table 7. Pad Function Descriptions

Pad No.

Mnemonic

Description

1

RFIN

RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.

2, 6

Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers. See Figure 4 for

the interface schematic.

3, 4, 5, 7

Top Edge Drain Bias Voltage Pads for the Amplifiers. External bypass capacitors are required on

3.5 V supply. See Figure 5 for the interface schematic.

8

RFOUT

RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 9 for the interface schematic.

9

DC Voltage Representing the RF Output Power. The voltage is rectified by the diode that is

biased through external resistor. See Figure 9 for the interface schematic.

10

interface schematic.

11, 13, 14, 15

Bottom Edge Drain Bias Voltage Pads for Amplifiers. External bypass capacitors are required on

3.5 V supply. See Figure 7 for the interface schematic.

12, 16

Gate Bias Voltage Pads for the First, Second, Third, and Fourth Stage Amplifiers, Alternative Bias

Configuration. See Figure 8 for the interface schematic.

Die Bottom

GND

Ground. Die bottom must be connected to RF and dc ground. See Figure 6 for the interface

schematic.