LT3476 datasheet(16/36 Pages) AD

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LT3966

Rev. 0

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Figure 8.

Figure 9.

COUNTER

DIM[12:0]

VARIABLE LENGTH

(6–13 BITS) COMPARE

SCL[2:0]

BAM

3966 F09

DIMMING GENERATOR

PWMOUT

3966 F10

PWM

BAM

Figure 10.

3966 F08

LT3966

PWM

CTRL/

PWM

INTVCC

APPLICATIONS INFORMATION

It is important to note that both the DIMEN signal and

the CTRL/PWM pin have the ability to clear the dimming

generator’s counter. This is advantageous when using a

combination of internal dimming and external ON/OFF

control with CTRL/PWM. By restarting the dimming gen-

erator’s counter in sync with the external ON/OFF signal,

light output remains flicker free from full duty cycle to zero.

The CTRL/PWM threshold for PWM dimming is 0.1V. For

simple on/off control, the PWM pin can be driven with any

standard logic signal between 1.5V and 5V. For dimming

with analog control, drive the pin with a DAC providing

output shutdown, or simply shunt a resistor divider using

a small NMOS transistor (Figure 8).

The internal dimming generator is based on a vari-

able-length counter updated at the master clock rate, deter-

mined by RT. An overview of the logic is shown in Figure 9.

The scale (SCL[2:0]) bits set the compare length and cycle

length of the dimming generator, from 6-bit at SCL = 000b,

to 13-bit at SCL = 111b. This cycle length determines

the dimming resolution, and also the dimming frequency

based on the MCLK value set by RT, Equation 4.

fDIM =

fSW

2(6+SCL)

(4)

For example, a 13-bit dimming cycle using SCL = 111b

would provide 8192:1 resolution at a dimming frequency

of 244Hz using a 2MHz MCLK frequency (RT = 47.5k).

The DIM[12:0] and BAM registers control the duty

cycle and modulation strategy of the dimming genera-

tor. In PWM (Pulse-Width Modulation) dimming mode

(BAM = 0), the PWMOUT signal is high while the value

in the DIM register is greater than the Counter. In BAM

(Bit-Angle Modulation) mode, the PWMOUT signal is high

anytime the MSB of the Counter matches the position of

a 1 in the value in the DIM register.

A comparison of the resulting waveforms of each of these

strategies is shown in Figure 10. For a DIM value of 13,

PWM mode provides a single pulse of 13 clock cycles

starting at the 1st counter cycle. BAM mode provides

pulses of duration 1, 4, and 8 cycles at the 1st, 4th, and

8th counter cycle, respectively. The total pulse duration

in BAM mode still equals 13-clock cycles.

The duty cycle of the dimming generator can be com-

puted using Equation 5.

Duty

DIM

2(6+SCL)

(5)

The system should be aware of the counter scale as

defined by SCL, and avoid writing DIM values larger than

the maximum value of counter. In the case where a DIM

value is larger than the counter range, the DIM value will

be truncated below bit (6+SCL). A DIM value of 0 0000

0000 0001 would be interpreted as 0 in all cases except

SCL = 111b.

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