LT1168 datasheet(19/28 Pages) AD

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LT6372-1

Rev. 0

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APPLICATIONS INFORMATION

Split Reference Pins

Output Level Shifting with the LT6372-1’s difference ampli-

fier features split reference pins, REF1 and REF2, which

allow the output to be easily and accurately level shifted

without the use of external circuitry. REF1 and REF2 are

typically tied to an ADC ground and reference respectively.

In this configuration the amplifier’s output is conveniently

level shifted to the center of the ADC input range.

If REF1 and REF2 are shorted to each other, they can

function as the reference for the output voltage like a tra-

ditional instrumentation amplifier.

Parasitic resistance in series with REF1 and REF2 should

be minimized to preserve CMRR and gain performance.

It is also important to note that the drift in any circuitry

used to drive REF1 or REF2 can results in an additional

output drift term. Therefore, it may be important to con-

sider the temperature accuracy of the circuitry used to

drive the REF pin.

Gain Setting Resistor Connections

Each pre-amplifier gives a set of RG connection termi-

nals which should be routed separately to the gain setting

resistor. Doing this minimizes the impact which parasitic

trace and lead resistance has on gain accuracy. When

routing to the gain setting resistors, large loops should

be avoided as they can couple noise into the amplifier.

Output Clamps

The CLHI and CLLO clamp pins limit the output voltage

swing of the LT6372-1. CLHI and CLLO are typically tied

to the ADC supply/reference and ADC ground respectively.

In this case the ADC input is protected from being over-

driven by the LT6372-1 which is likely running off a higher

supply voltage.

When the CLLO is tied to 0V, attempts to drive the output

below 0V will be clamped at –0.45 typically. When CLHI

is tied to 5V, attempts to drive the output above 5V will

be clamped at 5.45V typically.

CLHI and CLLO are high impedance inputs and do not

conduct significant current during clamping. Rather, inter-

nal amplifier nodes are controlled by CLHI and CLLO to

limit the output voltage.

In applications where clamping is not desired, CLLO

should be tied to V– and CLHI to V+ to disable clamping.

Input and Output Offset Voltage

The offset voltage of the LT6372-1 has two main compo-

nents: the input offset voltage due to the input amplifiers

and the output offset due to the output amplifier. The total

offset voltage referred to the input (RTI) is found by divid-

ing the output offset by the programmed gain and adding

it to the input offset voltage. At high gains the input offset

voltage dominates, whereas at low gains the output offset

voltage dominates. The total offset voltage is:

Total input offset voltage (RTI) = VOSI + VOSO/G

Total output offset voltage (RTO) = VOSI • G + VOSO

The preceding equations can also be used to calculate

offset drift in a similar manner.

Output Offset Trimming

The LT6372-1 is laser trimmed for low offset voltage

so that no external offset trimming is required for most

applications. In the event that the offset voltage needs

to be adjusted, the circuit in Figure 2 is an example of

an optional offset adjustment circuit. The op amp buffer

provides a low impedance signal to the REF pin in order

to achieve the best CMRR and lowest gain error.

Figure 2. Optional Trimming of Output Offset Voltage

LT6372-1 F02

–

REF1

REF2

OUTPUT

LT6372-1

10k

+10mV

100

–10mV

V–

V+

V–

V+

LTC2057

±5mV

ADJUSTMENT

RANGE

Thermocouple Effects

In order to achieve accuracy on the microvolt level, ther-

mocouple effects must be considered. Any connection

of dissimilar metals forms a thermoelectric junction and

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