LTC7151S datasheet(18/28 Pages) AD

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LTC3311S

Rev. A

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APPLICATIONS INFORMATION

pin is also actively pulled low during fault conditions: EN

pin is low, VIN is too low or in thermal shutdown.

For multiphase applications the PGOOD pin is used for

communication between the master and slave phases.

Connect the PGOOD pins together and pull-up to VIN or

VOUT with an external resistor.

Output Short Circuit Protection and Recovery

The peak inductor current at which the current compara-

tor shuts off the top power switch is controlled by the

voltage on the ITH pin. If the output current increases,

the error amplifier raises the ITH pin voltage until the

average inductor current matches the new load current.

In normal operation, the LTC3311S clamps the maximum

ITH pin voltage.

When the output is shorted to ground, the inductor cur-

rent decays very slowly during the switch off time because

of the low voltage across the inductor. To keep the current

in control, a secondary limit is also imposed on the valley

inductor current. If the inductor current measured through

the bottom power switch increases beyond IVALLEY(MAX),

the top power switch will be held off and switching cycles

will be skipped until the inductor current is reduced.

Recovery from a short circuit can be abrupt and because

the output is shorted and below regulation the regulator

is requesting the maximum current to charge the output.

When the short circuit condition is removed, the induc-

tor current could cause an extreme voltage overshoot in

the output. The LTC3311S addresses this potential issue

by regulating the SSTT voltage just above the FB volt-

age anytime the output is out of regulation. Therefore,

a recovery from an output short circuit goes through a

soft-start cycle. The output ramp is controlled and the

overshoot is minimized.

Low EMI PCB Layout

The LTC3311S is specifically designed to minimize EMI/

EMC emissions and also to maximize efficiency when

switching at high frequencies. For optimal performance,

the LTC3311S requires the use of multiple VIN bypass

capacitors.

Many designs will benefit from an additional 0.22µF, 0402

ceramic capacitors placed between the larger bulk input

ceramic capacitors. If the additional 0.22µF capacitors are

not added to the layout then the bulk input ceramic capaci-

tors should be moved as close as to the VIN pin as possible.

To avoid noise coupling into FB, the resistor divider should

be placed near the FB and AGND pins and physically

close to the LTC3311S. The remote output and ground

traces should be routed together as a differential pair to

the remote output. These traces should be terminated as

close as physically possible to the remote output point

that is to be accurately regulated through remote differ-

ential sensing.

See Figure 4 for a recommended PCB layout.

Figure 4. Recommended PCB Layout for the LTC3311S

COUT1

COUT2

CIN1

CFF

CIN2

CIN4

CIN3

GND

TO VOUT & GND

REMOTE SENSE

GND

VIN

GROUND PLANE ON LAYER 2

VOUT

CSS

CC2

CC1

3311S 04

(OPT)

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